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2022年6月11日 (六) 23:17的版本

模板:Short description 模板:Use dmy dates The following is a list of 7400-series digital logic integrated circuits. In the mid-1960s, the original 7400-series integrated circuits were introduced by Texas Instruments with the prefix "SN" to create the name SN74xx. Due to the popularity of these parts, other manufacturers released pin-to-pin compatible logic devices and kept the 7400 sequence number as an aid to identification of compatible parts. However, other manufacturers use different prefixes and suffixes on their part numbers.

概述

一些TTL逻辑器件具有扩展的军事规格温度范围。这些部件在部件号中以 54 而不是 74 为前缀.<ref>{{

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德州仪器（TI）部件上短暂的64前缀表示工业温度范围;到1973年，这个前缀已经从TI文献中删除了。最新的7400系列部件采用CMOSS或BiCMOSS技术,而不是TTL制造。具有单个门电路的表面贴装器件（通常采用5或6引脚封装）以741G而不是74为前缀。

Some manufacturers released some 4000-series equivalent CMOS circuits with a 74 prefix, for example, the 74HC4066<ref>{{

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}}</ref> was a replacement for the 4066 with slightly different electrical characteristics (different power-supply voltage ratings, higher frequency capabilities, lower "on" resistances in analog switches, etc.). See List of 4000-series integrated circuits. Conversely, the 4000-series has "borrowed" from the 7400 series模板:Snd such as the CD40193 and CD40161 being pin-for-pin functional replacements for 74C193 and 74C161.

Older TTL parts made by manufacturers such as Signetics, Motorola, Mullard and Siemens may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8输入与非门 like a 7430.

A few alphabetic characters to designate a specific logic subfamily may immediately follow the 74 or 54 in the part number, e.g., 74LS74 for low-power Schottky. Some CMOS parts such as 74HCT74 for high-speed CMOS with TTL-compatible input thresholds are functionally similar to the TTL part. Not all functions are available in all families. The generic descriptive feature of these alphabetic characters was diluted by various companies participating in the market at its peak and are not always consistent especially with more recent offerings. The National Semiconductor trademarks of the words FAST<ref>{{

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}}</ref> and FACT <ref>{{

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}}</ref> are usually cited in the descriptions from other companies when describing their own unique designations.<ref>{{

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In a few instances, such as the 7478 and 74107, the same suffix in different families do not have completely equivalent logic functions.

Another extension to the series is the 7416xxx variant, representing mostly the 16-bit-wide counterpart of otherwise 8-bit-wide "base" chips with the same three ending digits. Thus e.g. a "7416373" would be the 16-bit-wide equivalent of a "74373". Some 7416xxx parts, however, do not have a direct counterpart from the standard 74xxx range but deliver new functionality instead, which needs making use of the 7416xxx series' higher pin count. For more details, refer primarily to the Texas Instruments documentation mentioned in the References section.

For CMOS (AC, HC, etc.) subfamilies, read "open drain" for "open collector" in the table below.

There are a few numeric suffixes that have multiple conflicting assignments, such as the 74453.

逻辑门

文件:Logique74ls51.svg

Schematic of 74LS51 IC consists of a 3-3 AOI gate and 2-2 AOI gate. AOI means AND-OR-Invert (AND-NOR). Most AOI chips are currently obsolete.

模板:See also 由于有许多种7400 系列芯片，为了更轻松地选择需要的芯片，以下对芯片类型进行分组（仅包括组合逻辑门）。

对于本节中的芯片编号，“x”表示 7400-series logic family，例如 LS、ALS、HCT、AHCT、HC、AHC、LVC 等。

Normal inputs / push–pull outputs

种类	缓冲器	非门
6个 1输入	74x34	74x04

种类	AND与门	NAND与非门	OR或门	NOR或非门	XOR异或门	XNOR异或非门
4个 2输入	74x08	74x00	74x32	74x02	74x86	74x7266
3个 3输入	74x11	74x10	74x4075	74x27	n/a	n/a
2个 4输入	74x21	74x20	74x4072	74x29	n/a	n/a
1个 8输入	n/a	74x30	74x4078	74x4078	n/a	n/a

Schmitt-trigger inputs / push–pull outputs

种类	缓冲器	非门
6个 1输入	74x7014	74x14

种类	AND与门	NAND与非门	OR或门	NOR或非门
4个 2输入	74x7001	74x132	74x7032	74x7002
2个 4输入	n/a	74x13	n/a	n/a

Normal inputs / open-collector outputs

种类	缓冲器	非门
6个 1输入	74x07	74x05

种类	AND与门	NAND与非门	OR或门	NOR或非门	XOR异或门	XNOR异或非门
4个 2输入	74x09	74x03	n/a	74x33	74x136	74x266
3个 3输入	74x15	74x12	n/a	n/a	n/a	n/a
2个 4输入	n/a	74x22	n/a	n/a	n/a	n/a

Schmitt-trigger inputs / three-state outputs

种类	缓冲器	非门
8个 1输入	74x241 74x244	74x240

AND-OR-invert (AOI) logic gates: NOTE: in past decades, a number of AND-OR-invert (AOI) parts were available in 7400 TTL families, but currently most are obsolete.

SN5450 = 2个 2-2 AOI gate, one is expandable (SN54 is military version of SN74)
SN74LS51 = 2-2 AOI gate and 3-3 AOI gate
SN54LS54 = single 2-3-3-2 AOI gate

较多pin脚的芯片

本节中的器件的引脚数为14个及以上。较小芯片编号是在20世纪60年代和70年代发布的，然后几十年来逐步有更高的芯片编号。IC制造商继续制造那些广泛使用的芯片，而其他许多芯片编号被认为是过时的，并不再生产了。较旧的芯片型号可能从有限的卖家处获得，比如 new old stock(NOS)即新的原始库存，尽管有些芯片型号更难找到。

对于下表：

芯片型号列模板:Snd "x"是 logic subfamily 的占位符. 例如，74x00芯片在“LS”逻辑系列中就是“74LS00”。
描述列模板:Snd 包括术语施密特触发器、集电极开路/漏极开路、三态被移动到输入列和输出列，以便更容易地按这些特征进行排序。
输入列模板:Snd 空白单元格表示正常输入。
输出列模板:Snd 空白单元格表示"totem pole" 输出，也称为 push–pull output，能够驱动同一逻辑子类芯片的十个标准输入 (fan-out N_O = 10). 具有更高输出电流的芯片型号通常称为驱动器或缓冲器。
Pin数目列模板:Snd 雙列直插封裝 (DIP) 封装的pin脚数目; 括号（圆括号）中的数字表示该 IC 没有已知的双列直插式封装版本。

模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x00	4	4个 2输入 NAND与非门			14	SN74LS00
74x01	4	4个 2输入 NAND与非门		open-collector	14	SN74LS01
74x02	4	4个 2输入 NOR 或非门			14	SN74LS02
74x03	4	4个 2输入 NAND与非门		open-collector	14	SN74LS03
74x04	6	6个非门			14	SN74LS04
74x05	6	6个非门		open-collector	14	SN74LS05
74x06	6	6个非门		open-collector 30 V / 40 mA	14	SN74LS06
74x07	6	6个 buffer gate		open-collector 30 V / 40 mA	14	SN74LS07
74x08	4	4个 2输入 AND gate			14	SN74LS08
74x09	4	4个 2输入 AND与门		open-collector	14	SN74LS09
74x10	3	3个 3输入 NAND与非门			14	SN74LS10
74x11	3	3个 3输入 AND与门			14	SN74LS11
74x12	3	3个 3输入 NAND与非门		open-collector	14	SN74LS12
74x13	2	2个 4输入 NAND与非门	Schmitt trigger		14	SN74LS13
74x14	6	6个非门	Schmitt trigger		14	SN74LS14
74x15	3	3个 3输入 AND与门		open-collector	14	SN74LS15
74x16	6	6个非门		open-collector 15 V / 40 mA	14	SN7416
74x17	6	6个 buffer gate		open-collector 15 V / 40 mA	14	SN7417
74x18	2	2个 4输入 NAND与非门	Schmitt trigger		14	SN74LS18
74x19	6	6个非门	Schmitt trigger		14	SN74LS19
74x20	2	2个 4输入 NAND与非门			14	SN74LS20
74x21	2	2个 4输入 AND与门			14	SN74LS21
74x22	2	2个 4输入 NAND与非门		open-collector	14	SN74LS22
74x23	2	2个 4输入 NOR 或非门 with strobe, one gate expandable with 74x60			16	SN7423
74x24	4	4个 2输入 NAND与非门	Schmitt trigger		14	SN74LS24
74x25	2	2个 4输入 NOR 或非门 with strobe			14	SN7425
74x26	4	4个 2输入 NAND与非门		open-collector 15 V	14	SN74LS26
74x27	3	3个 3输入 NOR 或非门			14	SN74LS27
74x28	4	4个 2输入 NOR 或非门		driver N_O=30	14	SN74LS28
74x29	2	2个 4输入 NOR 或非门			14	US7429A
74x30	1	1个 8输入 NAND与非门			14	SN74LS30
74x31	6	6个 delay elements (two 6ns, two 23-32ns, two 45-48ns)			16	SN74LS31
74x32	4	4个 2输入 OR gate			14	SN74LS32
74x33	4	4个 2输入 NOR 或非门		open-collector driver N_O=30	14	SN74LS33
74x34	6	6个 buffer gate			14	MM74HC34
74x35	6	6个 buffer gate		open-collector	14	SN74ALS35
74x36	4	4个 2输入 NOR 或非门 (different pinout than 7402)			14	SN74HC36
74x37	4	4个 2输入 NAND与非门		driver N_O=30	14	SN74LS37
74x38	4	4个 2输入 NAND与非门		open-collector driver N_O=30	14	SN74LS38
74x39	4	4个 2输入 NAND与非门 (different pinout than 7438)		open-collector 60 mA	14	SN7439
74x40	2	2个 4输入 NAND与非门		driver N_O=30	14	SN74LS40
74x41	1	BCD to decimal decoder / Nixie tube driver		open-collector 70 V	16	DM7441A
74x42	1	BCD to decimal decoder			16	SN74LS42
74x43	1	excess-3 to decimal decoder			16	SN7443A
74x44	1	Gray code to decimal decoder			16	SN7444A
74x45	1	BCD to decimal decoder/driver		open-collector 30 V / 80 mA	16	SN7445
74x46	1	BCD to 7-segment display decoder/driver		open-collector 30 V	16	SN7446A
74x47	1	BCD to 7-segment decoder/driver		open-collector 15 V	16	SN74LS47
74x48	1	BCD to 7-segment decoder/driver		open-collector, 2 kΩ pull-up	16	SN74LS48
74x49	1	BCD to 7-segment decoder/driver		open-collector	14	SN74LS49
74x50	2	2个 2-2输入 AND-OR-Invert gate, one gate expandable			14	SN7450
7451, 74H51, 74S51	2	2个 2-2输入 AND-OR-Invert (AOI) gate			14	SN7451
74L51, 74LS51	2	3-3输入 AND-OR-Invert gate and 2-2输入 AND-OR-Invert gate			14	SN74LS51
74x52	1	3-2-2-2输入 AND-OR gate, expandable with 74x61			14	SN74H52
7453	1	2-2-2-2输入 AND-OR-Invert gate, expandable			14	SN7453
74H53	1	3-2-2-2输入 AND-OR-Invert gate, expandable			14	SN74H53
7454	1	2-2-2-2输入 AND-OR-Invert gate			14	SN7454
74H54	1	3-2-2-2输入 AND-OR-Invert gate			14	SN74H54
74L54, 74LS54	1	3-3-2-2输入 AND-OR-Invert gate			14	SN74LS54
74x55	1	4-4输入 AND-OR-Invert gate, 74H55 is expandable			14	SN74LS55
74x56	1	50:1 frequency divider			8	SN74LS56
74x57	1	60:1 frequency divider			8	SN74LS57
74x58	2	3-3输入 AND-OR gate and 2-2输入 AND-OR gate			14	74HC58
74x59	2	2个 3-2输入 AND-OR-Invert gate			14	US7459A
74x60	2	2个 4输入 expander for 74x23, 74x50, 74x53, 74x55		模板:Unknown	14	SN7460
74x61	3	3个 3输入 expander for 74x52		模板:Unknown	14	SN74H61
74x62	1	3-3-2-2输入 AND-OR expander for 74x50, 74x53, 74x55		模板:Unknown	14	SN74H62
74x63	6	6个 current sensing interface gates	模板:Unknown		14	SN74LS63
74x64	1	4-3-2-2输入 AND-OR-Invert gate			14	SN74S64
74x65	1	4-3-2-2 input AND-OR-Invert gate		open-collector	14	SN74S65
74x67	1	AND与门d J-K master-slave flip-flop, asynchronous preset and clear (improved 74L72)			(16)	BL54L67Y
74L68	2	2个 J-K flip-flop, asynchronous clear (improved 74L73)			(18)	BL54L68Y
74LS68	2	2个 4-bit decade counters			16	SN74LS68
74L69	2	2个 J-K flip-flop, asynchronous preset, common clock and clear			(18)	BL54L69Y
74LS69	2	2个 4-bit binary counters			16	SN74LS69
74x70	1	AND-gated positive edge triggered J-K flip-flop, asynchronous preset and clear			14	SN7470
74H71	1	AND-OR-gated J-K master-slave flip-flop, preset			14	SN74H71
74L71	1	AND-gated R-S master-slave flip-flop, preset and clear			14	SN54L71
74x72	1	AND与门d J-K master-slave flip-flop, asynchronous preset and clear			14	SN7472
74x73	2	2个 J-K flip-flop, asynchronous clear			14	SN54LS73A
74x74	2	2个 D positive edge triggered flip-flop, asynchronous preset and clear			14	SN74LS74A
74x75	2	4-bit bistable latch, complementary outputs			16	SN74LS75
74x76	2	2个 J-K flip-flop, asynchronous preset and clear			16	SN74LS76A
74x77	1	4-bit bistable latch			14	SN74LS77
74H78	2	2个 positive pulse triggered J-K flip-flop, preset, common clock and common clear			14	SN74H78
74L78	2	2个 positive pulse triggered J-K flip-flop, preset, common clock and common clear			14	SN54L78
74LS78	2	2个 negative edge triggered J-K flip-flop, preset, common clock and common clear			14	SN74LS78A
74x79	2	2个 D positive edge triggered flip-flop, asynchronous preset and clear			14	MC7479
74x80	1	gated full adder			14	SN7480
74x81	1	16-bit RAM			14	SN7481A
74x82	1	2-bit binary full adder			14	SN7482
74x83	1	4-bit binary full adder			16	SN74LS83A
74x84	1	16-bit RAM			16	SN7484A
74x85	1	4-bit magnitude comparator			16	SN74LS85
74x86	4	4个 2输入 XOR gate			14	SN74LS86A
74x87	1	4-bit true/complement/zero/one element			14	SN74H87
74x88	1	256-bit ROM (32x8)		open-collector	16	SN7488A
74x89	1	64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs		open-collector	16	SN7489
74x90	1	decade counter (separate divide-by-2 and divide-by-5 sections)			14	SN74LS90
74x91	1	8-bit shift register, serial in, serial out, gated input			14	SN74LS91
74x92	1	divide-by-12 counter (separate divide-by-2 and divide-by-6 sections)			14	SN74LS92
74x93	1	4-bit binary counter (separate divide-by-2 and divide-by-8 sections); different pinout for 74L93			14	SN74LS93
74x94	1	4-bit shift register, 2个 asynchronous presets			16	SN7494
74x95	1	4-bit shift register, parallel in, parallel out, serial input; different pinout for 74L95			14	SN74LS95B
74x96	1	5-bit parallel-in/parallel-out shift register, asynchronous preset			16	SN74LS96
74x97	1	synchronous 6-bit binary rate multiplier			16	SN7497
74x98	1	4-bit data selector/storage register			16	SN54L98
74x99	1	4-bit bidirectional universal shift register			16	SN54L99
模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x100	2	2个 4-bit bistable latch			24	SN74100
74x101	1	AND-OR-gated J-K negative-edge-triggered flip-flop, preset			14	SN74H101
74x102	1	AND-gated J-K negative-edge-triggered flip-flop, preset and clear			14	SN74H102
74x103	2	2个 J-K negative-edge-triggered flip-flop, clear			14	SN74H103
74x104	1	J-K master-slave flip-flop			14	SN74104
74x105	1	J-K master-slave flip-flop, J2 and K2 inverted			14	SN74105
74x106	2	2个 J-K negative-edge-triggered flip-flop, preset and clear			16	SN74H106
74x107	2	2个 J-K flip-flop, clear			14	SN74107
74x107A	2	2个 J-K negative-edge-triggered flip-flop, clear			14	SN74LS107A
74x108	2	2个 J-K negative-edge-triggered flip-flop, preset, common clear and common clock			14	SN74H108
74x109	2	2个 J-NotK positive-edge-triggered flip-flop, clear and preset			16	SN74109
74x110	1	AND-gated J-K master-slave flip-flop, data lockout			14	SN74110
74x111	2	2个 J-K master-slave flip-flop, data lockout, reset, set			16	TL74111N
74x112	2	2个 J-K negative-edge-triggered flip-flop, clear and preset			16	SN74LS112A
74x113	2	2个 J-K negative-edge-triggered flip-flop, preset			14	SN74LS113A
74x114	2	2个 J-K negative-edge-triggered flip-flop, preset, common clock and clear			14	SN74LS114A
74x115	2	2个 J-K master-slave flip-flop, data lockout, reset			14	TL74115N
74116, 74L116	2	2个 4-bit latch, clear			24	SN74116 <ref name=ttltb1>模板:Cite book</ref>模板:Rp
74H116	1	AND-gated J-K flip flop	模板:Unknown	模板:Unknown	14	MC74H116
74x117	1	AND-gated J-K flip flop, one J and K input inverted	模板:Unknown	模板:Unknown	14	MC74H117
74x118	6	6个 set/reset latch, common reset			16	ITT74118
74119	6	6个 set/reset latch			24	TL74119N <ref name=ttltb1/>模板:Rp
74H119	2	2个 J-K flip-flop, shared clear and clock inputs	模板:Unknown	模板:Unknown	14	MC74H119
74120	2	2个 pulse synchronizer/drivers	15 kΩ pull-up		16	SN74120
74H120	2	2个 J-K flip-flop, separate clock inputs	模板:Unknown	模板:Unknown	14	MC74H120
74x121	1	monostable multivibrator	Schmitt trigger		14	SN74121
74x122	1	retriggerable monostable multivibrator, clear			14	SN74122
74x123	2	2个 retriggerable monostable multivibrator, clear			16	SN74123
74x124	2	2个 voltage-controlled oscillator	analog		16	SN74S124
74x125	4	4个 bus buffer, negative enable		三态逻辑	14	SN74LS125A
74x126	4	4个 bus buffer, positive enable		三态逻辑	14	SN74LS126A
74x128	4	4个 2输入 NOR 或非门		driver 50 Ω	14	SN74128
74x130	2	retriggerable monostable multivibrator			16	SN74130
74131	4	4个 2输入 AND与门		open-collector 15 V	14	ITT74131
74AS131, 74ALS131	1	3-to-8 line decoder/demultiplexer, address register, inverting outputs			16	SN74AS131
74x132	4	4个 2输入 NAND与非门	Schmitt trigger		14	SN74LS132
74x133	1	1个 13输入 NAND与非门			16	SN54ALS133
74x134	1	1个 12输入 NAND与非门		三态逻辑	16	SN74S134
74x135	4	4个 XOR异或门/XNOR异或非门, two inputs to select logic type			16	SN74S135
74x136	4	4个 2输入 XOR gate		open-collector	14	SN74LS136
74x137	1	3-to-8 line decoder/demultiplexer, address latch, inverting outputs			16	SN74LS137
74x138	1	3-to-8 line decoder/demultiplexer, inverting outputs			16	SN74LS138
74x139	2	2个 2-to-4 line decoder/demultiplexer, inverting outputs			16	SN74LS139A
74x140	2	2个 4输入 NAND与非门		driver 50 Ω	14	SN74S140
74x141	1	BCD to decimal decoder/driver for cold-cathode indicator / Nixie tube		open-collector 60 V	16	DM74141
74x142	1	decade counter/latch/decoder/driver for Nixie tubes		open-collector 60 V	16	SN74142
74x143	1	decade counter/latch/decoder/7-segment driver		constant current 15 mA	24	SN74143
74x144	1	decade counter/latch/decoder/7-segment driver		open-collector 15 V / 25 mA	24	SN74144
74x145	1	BCD to decimal decoder/driver		open-collector 15 V / 80 mA	16	SN74145
74x146	1	3-to-8 line decoder			模板:Unknown	MCE74H146
74x147	1	10-line to 4-line priority encoder			16	SN74147
74x148	1	8-line to 3-line priority encoder			16	SN74148
74x149	1	8-line to 8-line priority encoder			20	MM74HCT149
74x150	1	16-line to 1-line data selector/multiplexer			24	SN74150
74x151	1	8-line to 1-line data selector/multiplexer			16	SN74151A
74x152	1	8-line to 1-line data selector/multiplexer, inverting output			14	SN54152A
74x153	2	2个 4-line to 1-line data selector/multiplexer, non-inverting outputs			16	SN74153
74x154	1	4-to-16 line decoder/demultiplexer, inverting outputs			24	SN74154
74x155	2	2个 2-to-4 line decoder/demultiplexer, inverting outputs			16	SN74155
74x156	2	2个 2-to-4 line decoder/demultiplexer, inverting outputs		open-collector	16	SN74156
74x157	4	4个 2-line to 1-line data selector/multiplexer, non-inverting outputs			16	SN74157
74x158	4	4个 2-line to 1-line data selector/multiplexer, inverting outputs			16	SN74LS158
74x159	1	4-to-16 line decoder/demultiplexer		open-collector	24	SN74159
74x160	1	synchronous presettable 4-bit decade counter, asynchronous clear			16	SN74160
74x161	1	synchronous presettable 4-bit binary counter, asynchronous clear			16	SN74161
74x162	1	synchronous presettable 4-bit decade counter, synchronous clear			16	SN74162
74x163	1	synchronous presettable 4-bit binary counter, synchronous clear			16	SN74163
74x164	1	8-bit serial-in parallel-out (SIPO) shift register, asynchronous clear, not output latch			14	SN74164
74x165	1	8-bit parallel-in serial-out (PISO) shift register, parallel load, complementary outputs			16	SN74165
74x166	1	parallel-load 8-bit shift register			16	SN74166
74x167	1	synchronous decade rate multiplier			16	SN74167
74x168	1	synchronous presettable 4-bit up/down decade counter			16	DM74LS168
74x169	1	synchronous presettable 4-bit up/down binary counter			16	SN74LS169B
74x170	1	16-bit register file (4x4)		open-collector	16	SN74170
74x171	4	4个 D flip-flops, clear			16	SN74LS171
74x172	1	16-bit multiple port register file (8x2)		三态逻辑	24	SN74172
74x173	4	4个 D flip-flop, asynchronous clear		三态逻辑	16	SN74173
74x174	6	6个 D flip-flop, common asynchronous clear			16	SN74174
74x175	4	4个 D edge-triggered flip-flop, complementary outputs and asynchronous clear			16	SN74175
74x176	1	presettable decade (bi-quinary) counter/latch			14	SN74176
74x177	1	presettable binary counter/latch			14	SN74177
74x178	1	4-bit parallel-access shift register			14	SN74178
74x179	1	4-bit parallel-access shift register, asynchronous clear input, complementary Q_d output			16	SN74179
74x180	1	9-bit odd/even parity bit generator and checker			14	SN74180
74x181	1	4-bit arithmetic logic unit and function generator			24	SN74LS181
74x182	1	lookahead carry generator			16	SN74S182
74x183	2	2个 carry-save full adder			14	SN74LS183
74x184	1	BCD to binary converter		open-collector	16	SN74184
74x185	1	6-bit binary to BCD converter		open-collector	16	SN74185A
74x186	1	512-bit ROM (64x8)		open-collector	24	SN74186
74x187	1	1024-bit ROM (256x4)		open-collector	16	SN74187
74x188	1	256-bit PROM (32x8)		open-collector	16	SN74S188
74x189	1	64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs		三态逻辑	16	SN74S189
74x190	1	synchronous presettable up/down 4-bit decade counter			16	SN74190
74x191	1	synchronous presettable up/down 4-bit binary counter			16	SN74191
74x192	1	synchronous presettable up/down 4-bit decade counter, clear			16	SN74192
74x193	1	synchronous presettable up/down 4-bit binary counter, clear			16	SN74193
74x194	1	4-bit bidirectional universal shift register			16	SN74194
74x195	1	4-bit parallel-access shift register			16	SN74195
74x196	1	presettable 4-bit decade counter/latch			14	SN74196
74x197	1	presettable 4-bit binary counter/latch			14	SN74197
74x198	1	8-bit bidirectional universal shift register			24	SN74198
74x199	1	8-bit universal shift register, J-NotK serial inputs			24	SN74199
模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x200	1	256-bit RAM (256x1)		三态逻辑	16	DM74S200
74x201	1	256-bit RAM (256x1)		三态逻辑	16	SN74S201
74x202	1	256-bit RAM (256x1) with power down		三态逻辑	16	SN74LS202
74x206	1	256-bit RAM (256x1)		open-collector	16	DM74S206
74x207	1	1024-bit RAM (256x4)		三态逻辑	16	SN74LS207
74x208	1	1024-bit RAM (256x4), separate data in- and outputs		三态逻辑	20	SN74LS208
74x209	1	1024-bit RAM (1024x1)		三态逻辑	16	SN74S209
74x210	8	8个 buffer, inverting		三态逻辑	20	SN74LS210
74x211	1	144-bit RAM (16x9) with output latch		三态逻辑	20	74F211
74x212	1	144-bit RAM (16x9)		三态逻辑	20	74F212
74x213	1	192-bit RAM (16x12)		三态逻辑	20	74F213
74x214	1	1024-bit RAM (1024x1)		三态逻辑	16	SN74LS214
74x215	1	1024-bit RAM (1024x1) with power-down mode		三态逻辑	16	SN74LS215
74x216	1	256-bit RAM (64x4), common I/O		三态逻辑	16	SN74LS216
74x217	1	256-bit RAM (64x4)		三态逻辑	20	SN74ALS217
74x218	1	256-bit RAM (32x8)		三态逻辑	20	SN74ALS218
74x219	1	64-bit RAM (16x4), non-inverting outputs		三态逻辑	16	SN74LS219
74x221	2	2个 monostable multivibrator	Schmitt trigger		16	SN74221
74x222	1	64-bit FIFO memory (16x4), synchronous, input/output ready enable		三态逻辑	20	SN74LS222
74x224	1	64-bit FIFO memory (16x4), synchronous		三态逻辑	16	SN74LS224
74x225	1	80-bit FIFO memory (16x5), asynchronous		三态逻辑	20	SN74S225
74x226	1	4-bit parallel latched bus transceiver		三态逻辑	16	SN74S226
74x227	1	64-bit FIFO memory (16x4), synchronous, input/output ready enable		open-collector	20	SN74LS727
74x228	1	64-bit FIFO memory (16x4), synchronous		open-collector	20	SN74LS728
74x229	1	80-bit FIFO memory (16x5), asynchronous		三态逻辑	20	SN74ALS229B
74x230	2	2个 4-bit buffer/driver, one inverted, one non-inverted; negative enable		三态逻辑	20	SN74AS230
74x231	2	2个 4-bit buffer/driver, both inverted; one positive and one negative enable		三态逻辑	20	SN74AS231
74x232	1	64-bit FIFO memory (16x4), asynchronous		三态逻辑	16	SN74ALS232B
74x233	1	80-bit FIFO memory (16x5), asynchronous		三态逻辑	20	SN74ALS233B
74x234	1	256-bit FIFO memory (64x4), asynchronous		三态逻辑	16	SN74ALS234
74x235	1	320-bit FIFO memory (64x5), asynchronous		三态逻辑	20	SN74ALS235
74x236	1	256-bit FIFO memory (64x4), asynchronous		三态逻辑	16	SN74ALS236
74x237	1	3-to-8 line decoder/demultiplexer, address latch, active high outputs			16	CD74HC237
74x238	1	3-to-8 line decoder/demultiplexer, active high outputs			16	CD74HC238
74x239	2	2个 2-to-4 line decoder/demultiplexer, active high outputs			16	SN74HC239
74x240	8	8个 buffer, inverting outputs	Schmitt trigger	三态逻辑	20	SN74LS240
74x241	8	8个 buffer, non-inverting outputs	Schmitt trigger	三态逻辑	20	SN74LS241
74x242	4	4个 bus transceiver, inverting outputs	Schmitt trigger	三态逻辑	14	SN74LS242
74x243	4	4个 bus transceiver, non-inverting outputs	Schmitt trigger	三态逻辑	14	SN74LS243
74x244	8	8个 buffer, non-inverting outputs	Schmitt trigger	三态逻辑	20	SN74LS244
74x245	8	8个 bus transceiver, non-inverting outputs	Schmitt trigger	三态逻辑	20	SN74LS245
74x246	1	BCD to 7-segment decoder/driver		open-collector 30 V	16	SN74246
74x247	1	BCD to 7-segment decoder/driver		open-collector 15 V	16	SN74247
74x248	1	BCD to 7-segment decoder/driver		open-collector, 2 kΩ pull-up	16	SN74248
74x249	1	BCD to 7-segment decoder/driver		open-collector	16	SN74249
74x250	1	1 of 16 data selector/multiplexer		三态逻辑	24	SN74AS250
74x251	1	8-line to 1-line data selector/multiplexer, complementary outputs		三态逻辑	16	SN74251
74x253	2	2个 4-line to 1-line data selector/multiplexer		三态逻辑	16	SN74LS253
74x255	2	2个 2-to-4 line decoder/demultiplexer, inverting outputs		三态逻辑	16	74LS255
74x256	2	2个 4-bit addressable latch			16	MC74F256
74x257	4	4个 2-line to 1-line data selector/multiplexer, non-inverting outputs		三态逻辑	16	SN74LS257B
74x258	4	4个 2-line to 1-line data selector/multiplexer, inverting outputs		三态逻辑	16	SN74LS258B
74x259	1	8-bit bit addressable input latch with clr			16	SN74259
74x260	2	2个 5输入 NOR 或非门			14	SN74LS260
74x261	1	2-bit by 4-bit parallel binary multiplier			16	SN74LS261
74x262	1	5760-bit ROM (Teletext character set, 128 characters 5x9)		三态逻辑	20	SN74S262N
74x264	1	look ahead carry generator			16	SN74AS264
74x265	4	4个 complementary output elements			16	SN74265
74x266	4	4个 2输入 XNOR异或非门		open-collector	14	SN74LS266
74x268	6	6个 D-type latches, common output control, common enable		三态逻辑	16	SN74S268
74x269	1	8-bit bidirectional binary counter			24	MC74F269
74x270	1	2048-bit ROM (512x4)		open-collector	16	SN74S270
74x271	1	2048-bit ROM (256x8)		open-collector	20	SN74S271
74x273	1	8-bit register, asynchronous clear			20	SN74273
74x274	1	4-bit by 4-bit binary multiplier		三态逻辑	20	SN74S274
74x275	1	7-bit slice Wallace tree		三态逻辑	16	SN74S275
74x276	4	4个 J-NotK edge-triggered flip-flops, separate clocks, common preset and clear			20	SN74276
74x278	1	4-bit cascadeable priority registers, latched data inputs			14	SN74278
74x279	4	4个 set-reset latch			16	SN74279
74x280	1	9-bit odd/even parity bit generator/checker			14	SN74LS280
74x281	1	4-bit parallel binary accumulator			24	SN74S281
74x282	1	look-ahead carry generator, selectable carry inputs			20	SN74AS282
74x283	1	4-bit binary full adder (has carry in function)			16	SN74283
74x284	1	4-bit by 4-bit parallel binary multiplier (low order 4 bits of product)			16	SN74284
74x285	1	4-bit by 4-bit parallel binary multiplier (high order 4 bits of product)			16	SN74285
74x286	1	9-bit parity generator/checker, bus driver parity I/O port			14	SN74AS286
74x287	1	1024-bit PROM (256x4)		三态逻辑	16	SN74S287
74x288	1	256-bit PROM (32x8)		三态逻辑	16	SN74S288
74x289	1	64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs		open-collector	16	SN74S289
74x290	1	decade counter (separate divide-by-2 and divide-by-5 sections)			14	SN74290
74x292	1	programmable frequency divider/digital timer			16	SN74LS292
74x293	1	4-bit binary counter (separate divide-by-2 and divide-by-8 sections)			14	SN74293
74x294	1	programmable frequency divider/digital timer			16	SN74LS294
74x295	1	4-bit bidirectional shift register		三态逻辑	14	SN74LS295B
74x297	1	digital phase-locked loop filter			16	SN74LS297
74x298	4	4个 2输入 multiplexer, storage			16	SN74298
74x299	1	8-bit bidirectional universal shift/storage register		三态逻辑	20	SN74LS299
模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x300	1	256-bit RAM (256x1)		open-collector	16	SN74LS300A
74x301	1	256-bit RAM (256x1)		open-collector	16	SN74S301
74x302	1	256-bit RAM (256x1)		open-collector	16	SN74LS302
74x303	1	8个 divide-by-2 clock driver, 2 outputs inverted			16	SN74AS303
74x304	1	8个 divide-by-2 clock driver			16	SN74AS304
74x305	1	8个 divide-by-2 clock driver, 4 outputs inverted			16	SN74AS305
74x309	1	1024-bit RAM (1024x1)		open-collector	16	SN74S309
74x310	8	8个 buffer, inverting	Schmitt trigger	三态逻辑	20	SN74LS310
74x311	1	144-bit RAM (16x9) with output latch		open-collector	20	74F311
74x312	1	144-bit RAM (16x9)		open-collector	20	74F312
74x313	1	192-bit RAM (16x12)		open-collector	20	74F313
74x314	1	1024-bit RAM (1024x1)		open-collector	16	SN74LS314
74x315	1	1024-bit RAM (1024x1) with power-down mode		open-collector	16	SN74LS315
74x316	1	256-bit RAM (64x4), common I/O		open-collector	16	SN74LS316
74x317	1	256-bit RAM (64x4)		open-collector	20	SN74ALS317
74x318	1	256-bit RAM (32x8)		open-collector	20	SN74ALS318
74x319	1	64-bit RAM (16x4)		open-collector	16	SN74LS319
74x320	1	crystal-controlled oscillator			16	SN74LS320
74x321	1	crystal-controlled oscillators, F/2 and F/4 count-down outputs			16	SN74LS320
74x322	1	8-bit shift register, sign extend		三态逻辑	20	SN74LS322A
74x323	1	8-bit bidirectional universal shift/storage register, synchronous clear		三态逻辑	20	SN74LS323
74x324	1	voltage-controlled oscillator (or crystal controlled), enable input, complementary outputs	analog		14	SN74LS324
74x325	2	2个 voltage-controlled oscillator (or crystal controlled), complementary outputs	analog		16	SN74LS325
74x326	2	2个 voltage-controlled oscillator (or crystal controlled), enable input, complementary outputs	analog		16	SN74LS326
74x327	2	2个 voltage-controlled oscillator (or crystal controlled)	analog		14	SN74LS327
74x330	1	PLA (12 inputs, 50 terms, 6 outputs)		三态逻辑	20	SN74S330
74x331	1	PLA (12 inputs, 50 terms, 6 outputs)		open-collector, 2.5 kΩ pull-up	20	SN74S331
74x333	1	PLA (12 inputs, 32 terms, 6 outputs, 4 state registers)		三态逻辑	24	SN74LS333
74x334	1	PLA (12 inputs, 32 terms, 6 outputs)		三态逻辑	24	SN74LS334
74x335	1	PLA (12 inputs, 32 terms, 6 outputs, 4 state registers)		open-collector	24	SN74LS335
74x336	1	PLA (12 inputs, 32 terms, 6 outputs)		open-collector	24	SN74LS336
74x337	1	clock driver		三态逻辑	20	SN74ABT337
74x340	8	8个 buffer, inverting outputs	Schmitt trigger	三态逻辑	20	SN74S340
74x341	8	8个 buffer, non-inverting outputs	Schmitt trigger	三态逻辑	20	SN74S341
74x344	8	8个 buffer, non-inverting outputs	Schmitt trigger	三态逻辑	20	SN74S344
74x347	1	BCD to 7-segment decoders/drivers, low voltage version of 7447		open-collector	16	SN74LS347
74x348	1	8 to 3-line priority encoder		三态逻辑	16	SN74LS348
74x350	1	4-bit shifter		三态逻辑	16	SN74S350
74x351	2	2个 8-line to 1-line data selectors/multiplexers, 4 common data inputs		三态逻辑	20	SN74351
74x352	2	2个 4-line to 1-line data selectors/multiplexers, inverting outputs			16	SN74LS352
74x353	2	2个 4-line to 1-line data selectors/multiplexers, inverting outputs		三态逻辑	16	SN74LS353
74x354	1	8-line to 1-line data selector/multiplexer, transparent registers		三态逻辑	20	CD74HC354
74x355	1	8-line to 1-line data selector/multiplexer, transparent registers		open-collector	20	SN74LS355
74x356	1	8-line to 1-line data selector/multiplexer, edge-triggered registers		三态逻辑	20	CD74HCT356
74x357	1	8-line to 1-line data selector/multiplexer, edge-triggered registers		open-collector	20	SN74LS357
74x361	1	bubble memory function timing generator			22	SN74LS361
74x362	1	four-phase clock generator/driver for Texas Instruments TMS9900			20	SN74LS362
74x363	1	8个 transparent latch		三态逻辑	20	SN74LS363
74x364	1	8个 edge-triggered D-type register		三态逻辑	20	SN74LS364
74x365	6	6个 buffer, non-inverting outputs		三态逻辑	16	SN74LS365A
74x366	6	6个 buffer, inverting outputs		三态逻辑	16	SN74HC366
74x367	6	6个 buffer, non-inverting outputs		三态逻辑	16	SN74LS367A
74x368	6	6个 buffer, inverting outputs		三态逻辑	16	SN74LS368A
74x370	1	2048-bit ROM (512x4)		三态逻辑	16	SN74S370
74x371	1	2048-bit ROM (256x8)		三态逻辑	20	SN74S371
74x373	8	8个 transparent latch		三态逻辑	20	SN74LS373
74x374	8	8个 register		三态逻辑	20	SN74LS374
74x375	4	4个 bistable latch			16	SN74LS375
74x376	4	4个 J-NotK flip-flop, common clock and common clear			16	SN74376
74x377	1	8-bit register, clock enable			20	SN74LS377
74x378	1	6-bit register, clock enable			16	SN74LS378
74x379	1	4-bit register, clock enable and complementary outputs			16	SN74LS379
74x380	1	8-bit multifunction register (combines features of x374, x377, x273, x534 ICs)		三态逻辑	24	SN74LS380
74x381	1	4-bit arithmetic logic unit/function generator, generate and propagate outputs			20	SN74LS381A
74x382	1	4-bit arithmetic logic unit/function generator, ripple carry and overflow outputs			20	SN74LS382
74x383	1	8-bit register		open-collector	20	SN74S383
74x384	1	8-bit by 1-bit two's complement multipliers			16	SN74LS384
74x385	4	4个 serial adder/subtractor			20	SN74LS385
74x386	4	4个 2输入 XOR gate			14	SN74LS386
74x387	1	1024-bit PROM (256x4)		open-collector	16	SN74S387
74x388	1	4-bit D-type register		三态逻辑 and standard	16	Am74S388
74x390	2	2个 4-bit decade counter			16	SN74LS390
74x393	2	2个 4-bit binary counter			14	SN74LS393
74x395	1	4-bit cascadable shift register		三态逻辑	16	SN74LS395A
74x396	8	8个 storage registers, parallel access			16	SN74LS396
74x398	4	4个 2输入 multiplexers, storage and complementary outputs			20	SN74LS398
74x399	4	4个 2输入 multiplexer, storage			16	SN74LS399
模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x401	1	CRC generator/checker			14	74F401
74x402	1	serial data polynomial generator/checker			16	74F402
74x403	1	64-bit FIFO memory (16x4)		三态逻辑	24	74F403
74x405	1	3-to-8 line decoder (equivalent to Intel 8205)			16	UCY74S405
74x406	1	3-to-8 line decoder	模板:Unknown	模板:Unknown	14	MC74406P
74x407	1	data access register		三态逻辑	24	74F407
74408	1	8-bit parity tree			14	MC74408
74S408	1	controller/driver for 16k/64k/256k dRAM			48	SN74S408
74x409	1	controller/driver for 16k/64k/256k dRAM			48	SN74S409
74x410	1	64-bit RAM (16x4) with output register		三态逻辑	18	74F410
74x411	1	FIFO RAM controller			40	74F411
74x412	1	multi-mode buffered 8-bit latches (equivalent to Intel 3212/8212)		三态逻辑	24	SN74S412
74x413	1	256-bit FIFO memory (64x4)			16	74F413
74x414	1	interrupt priority controller for Intel 8080 (equivalent to Intel 8214)			24	UCY74S414
74416	1	modulo 10 counter, preload and clear inputs			16	MC74416
74S416	1	4-bit bidirectional bus transceiver, non-inverting (equivalent to Intel 8216)		三态逻辑	16	UCY74S416
74x417	2	modulo 2 and modulo 5 counters, common preload and clear inputs			16	MC74417
74418	1	modulo 16 counter, preload and clear inputs			16	MC74418
74F418	1	32-bit error detection and correction circuit		三态逻辑	48	74F418
74419	2	2个 modulo 4 counters, common preload and clear inputs			16	MC74419
74S419	1	FIFO RAM controller			40	74S419
74x420	1	32-bit check bit / syndrome bit generator		三态逻辑	48	74F420
74x422	1	retriggerable monostable multivibrators, two inputs			14	SN74LS422
74x423	2	2个 retriggerable monostable multivibrator			16	SN74LS423
74x424	1	two-phase clock generator/driver for Intel 8080 (equivalent to Intel 8224)			16	SN74LS424
74x425	4	4个 bus buffers, active low enables		三态逻辑	14	SN74425
74x426	4	4个 bus buffers, active high enables		三态逻辑	14	SN74426
74x428	1	system controller for Intel 8080A (equivalent to Intel 8228)			28	SN74S428
74x429	1	FIFO RAM controller		三态逻辑	28	74LS429
74x430	1	cyclic redundancy checker/corrector			28	74F430
74x432	1	8-bit multi-mode buffered latch		三态逻辑	24	74F432
74x433	1	256-bit FIFO memory (64x4)		三态逻辑	24	74F433
74x436	1	line driver/memory driver circuits - MOS memory interface, damping output resistor			16	SN74S436
74x437	1	line driver/memory driver circuits - MOS memory interface			16	SN74S437
74x438	1	system controller for Intel 8080A (equivalent to Intel 8238)			28	SN74S438
74x440	4	4个 tridirectional bus transceiver, non-inverting outputs		open-collector	20	SN74LS440
74x441	4	4个 tridirectional bus transceiver, inverting outputs		open-collector	20	SN74LS441
74x442	4	4个 tridirectional bus transceiver, non-inverting outputs		三态逻辑	20	SN74LS442
74x443	4	4个 tridirectional bus transceiver, inverting outputs		三态逻辑	20	SN74LS443
74x444	4	4个 tridirectional bus transceiver, inverting and non-inverting outputs		三态逻辑	20	SN74LS444
74x445	1	BCD to decimal decoders/drivers		driver 80 mA	16	SN74LS445
74x446	4	4个 bus transceivers, direction controls, inverting outputs		三态逻辑	16	SN74LS446
74x447	1	BCD to 7-segment decoders/drivers, low voltage version of 74247		open-collector	16	SN74LS447
74x448	4	4个 tridirectional bus transceiver, inverting and non-inverting outputs		open-collector	20	SN74LS448
74x449	4	4个 bus transceivers, direction controls, non-inverting outputs		三态逻辑	16	SN74LS449
74450	1	counter, latch, 7-segment decoder	模板:Unknown	open-collector	16	MC74450
74S450	1	8192-bit PROM (1024x8) with power-down		三态逻辑	24	SN74S450
74LS450	1	16-to-1 multiplexer, complementary outputs			24	SN74LS450
74S451	1	8192-bit PROM (1024x8) with power-down		open-collector	24	SN74S451
74LS451	2	2个 8-to-1 multiplexer			24	SN74LS451
74x452	2	2个 decade counter, synchronous	模板:Unknown	模板:Unknown	16	MC74452
74453	2	2个 binary counter, synchronous	模板:Unknown	模板:Unknown	16	MC74453
74LS453	4	4个 4-to-1 multiplexer			24	SN74LS453
74x454	2	2个 decade up/down counter, synchronous, preset input	模板:Unknown	模板:Unknown	24	MC74454
74455	2	2个 binary up/down counter, synchronous, preset input	模板:Unknown	模板:Unknown	24	MC74455
74F455	1	8个 buffer / line driver with parity, inverting		三态逻辑	24	74F455
74456	1	4-bit NBCD full adder	模板:Unknown	模板:Unknown	16	MC74456
74F456	1	8个 buffer / line driver with parity, non-inverting		三态逻辑	24	74F456
74x458	1	nines complement / zero element	模板:Unknown	模板:Unknown	14	MC74458
74460	1	4-bit bus transfer switch	模板:Unknown	三态逻辑	16	MC74460
74LS460	1	10-bit comparator			24	SN74LS460
74x461	1	8-bit presettable binary counter		三态逻辑	24	SN74LS461
74x462	1	fiber-optic data-link transmitter		open-collector 100 mA and standard	20	SN74LS462
74x463	1	fiber-optic data-link receiver	analog		20	SN74LS463
74x465	8	8个 buffer, non-inverting outputs		三态逻辑	20	SN74LS465
74x466	8	8个 buffers, inverting outputs		三态逻辑	20	SN74LS466
74x467	8	8个 buffers, non-inverting outputs		三态逻辑	20	SN74LS467
74x468	8	8个 buffers, inverting outputs		三态逻辑	20	SN74LS468
74x469	1	8-bit synchronous up/down counter, parallel load and hold capability		三态逻辑	24	SN74LS469
74x470	1	2048-bit PROM (256x8)		open-collector	20	SN74S470
74x471	1	2048-bit PROM (256x8)		三态逻辑	20	SN74S471
74x472	1	4096-bit PROM (512x8)		三态逻辑	20	SN74S472
74x473	1	4096-bit PROM (512x8)		open-collector	20	SN74S473
74x474	1	4096-bit PROM (512x8)		三态逻辑	24	SN74S474
74x475	1	4096-bit PROM (512x8)		open-collector	24	SN74S475
74x476	1	4096-bit PROM (1024x4)		三态逻辑	18	SN74S476
74x477	1	4096-bit PROM (1024x4)		open-collector	18	SN74S477
74x478	1	8192-bit PROM (1024x8)		三态逻辑	24	SN74S478
74x479	1	8192-bit PROM (1024x8)		open-collector	24	SN74S479
74x480	1	1个 burst error recovery circuit			24	SN74S480
74x481	1	4-bit slice cascadable processor elements			(48)	SN74S481
74x482	1	4-bit slice expandable control elements			20	SN74S482
74x484	1	BCD-to-binary converter		三态逻辑	20	SN74S484A
74x485	1	binary-to-BCD converter		三态逻辑	20	SN74S485A
74x488	1	IEEE-488 bus interface			48	74ACT488
74x490	2	2个 decade counter			16	SN74490
74x491	1	10-bit binary up/down counter, limited preset		三态逻辑	24	SN74LS491
74x498	1	8-bit bidirectional shift register, parallel inputs		三态逻辑	24	SN74LS498
模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x500	1	6-bit flash analog-to-digital converter (ADC)	analog		24	74F500
74x502	1	8-bit successive approximation register			16	74LS502
74x503	1	8-bit successive approximation register with expansion control			16	74LS503
74x504	1	12-bit successive approximation register with expansion control			24	74LS504
74x505	1	8-bit successive approximation ADC	analog	三态逻辑	24	74F505
74x508	1	8-bit multiplier/divider			24	SN74S508
74x515	1	programmable mapping decoder (2-to-4 line decoder with 9 programmable enable inputs)			20	74HCT515<ref name=hcmostb>模板:Cite book</ref>模板:Rp
74x516	1	16-bit multiplier/divider			24	SN74S516
74x518	1	8-bit comparator	20 kΩ pull-up	open-collector	20	SN74ALS518
74x519	1	8-bit comparator		open-collector	20	SN74ALS519
74x520	1	8-bit comparator, inverting output	20 kΩ pull-up		20	SN74ALS520
74x521	1	8-bit comparator, inverting output			20	SN74ALS521
74x522	1	8-bit comparator, inverting output	20 kΩ pull-up	open-collector	20	SN74ALS522
74x524	1	8-bit registered comparator		open-collector	20	74F524
74x525	1	16-bit programmable counter			28	74F525
74x526	1	fuse programmable identity comparator, 16-bit			20	SN74ALS526
74x527	1	fuse programmable identity comparator, 8-bit + 4-bit conventional Identity comparator			20	SN74ALS527
74x528	1	fuse programmable Identity comparator, 12-bit			16	SN74ALS528
74x531	8	8个 transparent latch		三态逻辑	20	SN74S531
74x532	8	8个 register		三态逻辑	20	SN74S532
74x533	1	8个 transparent latch, inverting outputs		三态逻辑	20	CD74HC533
74x534	1	8个 register, inverting outputs		三态逻辑	20	CD74HC534
74x535	1	8个 transparent latch, inverting outputs		三态逻辑	20	SN74S535
74x536	1	8个 register, inverting outputs		三态逻辑	20	SN74S536
74x537	1	BCD to decimal decoder		三态逻辑	20	MC74F537
74x538	1	3-to-8 line decoder/demultiplexer		三态逻辑	20	SN74ALS538
74x539	2	2个 2-to-4 line decoder/demultiplexer		三态逻辑	20	SN74ALS539
74x540	1	8个非门	Schmitt trigger	三态逻辑	20	SN74LS540
74x541	1	8个 buffer gate	Schmitt trigger	三态逻辑	20	SN74LS541
74x543	1	8个 registered transceiver, non-inverting		三态逻辑	24	SN74F543
74x544	1	8个 registered transceiver, inverting		三态逻辑	24	MC74F544
74x545	1	8个 bidirectional transceiver, non-inverting		三态逻辑	20	74F545
74x546	1	8-bit bidirectional registered transceiver, non-inverting		三态逻辑	24	SN74LS546
74LS547	1	8-bit bidirectional latched transceiver, non-inverting		三态逻辑	24	SN74LS547
74F547	1	3-to-8 line decoder/demultiplexer with address latches and acknowledge output			20	74F547
74LS548	1	8-bit two-stage pipelined register		三态逻辑	24	SN74LS548
74F548	1	3-to-8 line decoder/demultiplexer with acknowledge output			20	74F548
74x549	1	8-bit two-stage pipelined latch		三态逻辑	24	SN74LS549
74x550	1	8个 registered transceiver with status flags, non-inverting		三态逻辑	28	74F550
74x551	1	8个 registered transceiver with status flags, inverting		三态逻辑	28	74F551
74x552	1	8个 registered transceiver with parity and flags		三态逻辑	28	74F552
74x556	1	16x16-bit multiplier slice		三态逻辑	(84)	74S556
74x557	1	8-bit by 8-bit multiplier		三态逻辑	40	SN74S557
74x558	1	8-bit by 8-bit multiplier		三态逻辑	40	SN74S558
74x559	1	8-bit expandable two's complement multiplier/divider		三态逻辑	24	74F559
74x560	1	4-bit decade counter		三态逻辑	20	SN74ALS560A
74x561	1	4-bit binary counter		三态逻辑	20	SN74ALS561A
74x563	1	8-bit D-type transparent latch, inverting outputs		三态逻辑	20	SN74ALS563B
74x564	1	8-bit D-type edge-triggered register, inverting outputs		三态逻辑	20	SN74ALS564B
74x566	1	8-bit bidirectional registered transceiver, inverting		三态逻辑	24	SN74LS566
74x567	1	8-bit bidirectional latched transceiver, inverting		三态逻辑	24	SN74LS567
74x568	1	decade up/down counter		三态逻辑	20	SN74ALS568A
74x569	1	binary up/down counter		三态逻辑	20	SN74ALS569A
74x570	1	2048-bit PROM (512x4)		open-collector	16	DM74S570
74x571	1	2048-bit PROM (512x4)		三态逻辑	16	DM74S571
74x572	1	4096-bit PROM (1024x4)		open-collector	18	DM74S572
74x573	1	8个 D-type transparent latch		三态逻辑	20	SN74ALS573C
74x574	1	8个 D-type edge-triggered flip-flop		三态逻辑	20	SN74HC574
74x575	1	8个 D-type edge-triggered flip-flop, synchronous clear		三态逻辑	24	SN74ALS575A
74x576	1	8个 D-type edge-triggered flip-flop, inverting outputs		三态逻辑	20	SN74ALS576B
74x577	1	8个 D-type edge-triggered flip-flop, synchronous clear, inverting outputs		三态逻辑	24	SN74ALS577A
74x579	1	8-bit bidirectional binary counter		三态逻辑	20	MC74F579
74x580	1	8个 D-type transparent latch, inverting outputs		三态逻辑	20	SN74ALS580B
74x582	1	4-bit BCD arithmetic logic unit			24	74F582
74x583	1	4-bit BCD adder			16	74F583
74x588	1	8个 bidirectional transceiver with IEEE-488 termination resistors		三态逻辑	20	74F588
74x589	1	8-bit shift register, input latch		三态逻辑	16	SN74LS589
74x590	1	8-bit binary counter, output registers		三态逻辑	16	SN74LS590
74x591	1	8-bit binary counter, output registers		open-collector	16	SN74LS591
74x592	1	8-bit binary counter, input registers			16	SN74LS592
74x593	1	8-bit binary counter, input registers		三态逻辑	20	SN74LS593
74x594	1	8-bit shift registers, Serial-In, Parallel-Out, output latches		buffered	16	SN74LS594
74x595	1	8-bit shift registers, Serial-In, Parallel-Out, output latches, output enable		三态逻辑	16	SN74LS595
74x596	1	8-bit shift registers, Serial-In, Parallel-Out, output latches, output enable		open-collector	16	SN74LS596
74x597	1	8-bit shift registers, Parallel-In, Serial-Out, input latches			16	SN74LS597
74x598	1	8-bit shift register, Selectable Parallel-In/Out input latches		三态逻辑	20	SN74LS598
74x599	1	8-bit shift registers, Serial-In, Parallel-Out, output latches		open-collector	16	SN74LS599
模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x600	1	dynamic memory refresh controller, transparent and burst modes, for 4K or 16K dRAM		三态逻辑	20	SN74LS600A
74x601	1	dynamic memory refresh controller, transparent and burst modes, for 64K dRAM		三态逻辑	20	SN74LS601A
74x602	1	dynamic memory refresh controller, cycle steal and burst modes, for 4K or 16K dRAM		三态逻辑	20	SN74LS602A
74x603	1	dynamic memory refresh controller, cycle steal and burst modes, for 64K dRAM		三态逻辑	20	SN74LS603A
74x604	1	8个 2输入 multiplexer, latch, high-speed		三态逻辑	28	SN74LS604
74x605	1	8个 2输入 multiplexer, latch, high-speed		open-collector	28	SN74LS605
74x606	1	8个 2输入 multiplexer, latch, glitch-free		三态逻辑	28	SN74LS606
74x607	1	8个 2输入 multiplexer, latch, glitch-free		open-collector	28	SN74LS607
74x608	1	memory cycle controller			16	SN74LS608
74x610	1	memory mapper, latched		三态逻辑	40	SN74LS610
74x611	1	memory mapper, latched		open-collector	40	SN74LS611
74x612	1	memory mapper		三态逻辑	40	SN74LS612
74x613	1	memory mapper		open-collector	40	SN74LS613
74x614	1	8个 bus transceiver and register, inverting		open-collector	24	SN74ALS614
74x615	1	8个 bus transceiver and register, non-inverting		open-collector	24	SN74ALS615
74x616	1	16-bit parallel error detection and correction		三态逻辑	40	SN74ALS616
74x617	1	16-bit parallel error detection and correction		open-collector	40	SN74ALS617
74x620	1	8个 bus transceiver, inverting		三态逻辑	20	SN74LS620
74x621	1	8个 bus transceiver, non-inverting		open-collector	20	SN74LS621
74x622	1	8个 bus transceiver, inverting		open-collector	20	SN74LS622
74x623	1	8个 bus transceiver, non-inverting		三态逻辑	20	SN74LS623
74x624	1	voltage-controlled oscillator, enable control, range control, two-phase outputs	analog		14	SN74LS624
74x625	2	2个 voltage-controlled oscillator, two-phase outputs	analog		16	SN74LS625
74x626	2	2个 voltage-controlled oscillator, enable control, two-phase outputs	analog		16	SN74LS626
74x627	2	2个 voltage-controlled oscillator	analog		14	SN74LS627
74x628	1	voltage-controlled oscillator, enable control, range control, external temperature compensation, two-phase outputs	analog		14	SN74LS628
74x629	2	2个 voltage-controlled oscillator, enable control, range control	analog		16	SN74LS629
74x630	1	16-bit error detection and correction (EDAC)		三态逻辑	28	SN74LS630
74x631	1	16-bit error detection and correction		open-collector	28	SN74LS631
74x632	1	32-bit parallel error detection and correction, byte-write		三态逻辑	52	SN74ALS632
74x633	1	32-bit parallel error detection and correction, byte-write		open-collector	52	SN74ALS633
74x634	1	32-bit parallel error detection and correction		三态逻辑	48	SN74ALS634
74x635	1	32-bit parallel error detection and correction		open-collector	48	SN74ALS635
74x636	1	8-bit parallel error detection and correction		三态逻辑	20	SN74LS636
74x637	1	8-bit parallel error detection and correction		open-collector	20	SN74LS637
74x638	1	8个 bus transceiver, inverting outputs		三态逻辑 and open-collector	20	SN74LS638
74x639	1	8个 bus transceiver, non-inverting outputs		三态逻辑 and open-collector	20	SN74LS639
74x640	1	8个 bus transceiver, inverting outputs		三态逻辑	20	SN74LS640
74x641	1	8个 bus transceiver, non-inverting outputs		open-collector	20	SN74LS641
74x642	1	8个 bus transceiver, inverting outputs		open-collector	20	SN74LS642
74x643	1	8个 bus transceiver, mix of inverting and non-inverting outputs		三态逻辑	20	SN74LS643
74x644	1	8个 bus transceiver, mix of inverting and non-inverting outputs		open-collector	20	SN74LS644
74x645	1	8个 bus transceiver, non-inverting outputs		三态逻辑	20	SN74LS645
74x646	1	8个 bus transceiver/latch/multiplexer, non-inverting outputs		三态逻辑	24	SN74ALS646A
74x647	1	8个 bus transceiver/latch/multiplexer, non-inverting outputs		open-collector	24	SN74LS647
74x648	1	8个 bus transceiver/latch/multiplexer, inverting outputs		三态逻辑	24	SN74ALS648A
74x649	1	8个 bus transceiver/latch/multiplexer, inverting outputs		open-collector	24	SN74LS649
74x651	1	8个 bus transceiver/register, inverting outputs		三态逻辑	24	SN74ALS651A
74x652	1	8个 bus transceiver/register, non-inverting outputs		三态逻辑	24	SN74ALS652A
74x653	1	8个 bus transceiver/register, inverting outputs		三态逻辑 and open-collector	24	SN74ALS653
74x654	1	8个 bus transceiver/register, non-inverting outputs		三态逻辑 and open-collector	24	SN74ALS654
74x655	1	8个 buffer / line driver with parity, inverting		三态逻辑	24	74F655
74x656	1	8个 buffer / line driver with parity, non-inverting		三态逻辑	24	74F656
74x657	1	8个 bidirectional transceiver with 8-bit parity generator/checker		三态逻辑	24	SN74F657
74x658	1	8个 bus transceiver, parity, inverting		三态逻辑	24	SN74HC658
74x659	1	8个 bus transceiver, parity, non-inverting		三态逻辑	24	SN74HC659
74x664	1	8个 bus transceiver, parity, inverting		三态逻辑	24	SN74HC664
74x665	1	8个 bus transceiver, parity, non-inverting		三态逻辑	24	SN74HC665
74x666	1	8-bit D-type transparent read-back latch, non-inverting		三态逻辑	24	SN74ALS666
74x667	1	8-bit D-type transparent read-back latch, inverting		三态逻辑	24	SN74ALS667
74x668	1	synchronous 4-bit decade up/down counter			16	SN74LS668
74x669	1	synchronous 4-bit binary up/down counter			16	SN74LS669
74x670	1	16-bit register file (4x4)		三态逻辑	16	SN74LS670
74x671	1	4-bit bidirectional shift register/latch/multiplexer, direct clear		三态逻辑	20	SN74LS671
74x672	1	4-bit bidirectional shift register/latch/multiplexer, synchronous clear		三态逻辑	20	SN74LS672
74x673	1	16-bit serial-in, serial/parallel-out shift register, output storage registers		三态逻辑	24	SN74LS673
74x674	1	16-bit parallel-in, serial-out shift register		三态逻辑	24	SN74LS674
74x675	1	16-bit serial-in, serial/parallel-out shift register			24	74F675A
74x676	1	16-bit serial/parallel-in, serial-out shift register			24	74F676
74x677	1	16-bit address comparator, enable			24	SN74ALS677
74x678	1	16-bit address comparator, latch			24	SN74ALS678
74x679	1	12-bit address comparator, latch			20	SN74ALS679
74x680	1	12-bit address comparator, enable			20	SN74ALS680
74x681	1	4-bit parallel binary accumulator		三态逻辑	20	SN74LS681
74x682	1	8-bit magnitude comparator, P>Q output	20 kΩ pull-up		20	SN74LS682
74x683	1	8-bit magnitude comparator, P>Q output	20 kΩ pull-up	open-collector	20	SN74LS683
74x684	1	8-bit magnitude comparator, P>Q output			20	SN74LS684
74x685	1	8-bit magnitude comparator, P>Q output		open-collector	20	SN74LS685
74x686	1	8-bit magnitude comparator, P>Q output, enable			24	SN74LS686
74x687	1	8-bit magnitude comparator, P>Q output, enable		open-collector	24	SN74LS687
74x688	1	8-bit magnitude comparator, enable			20	SN74LS688
74x689	1	8-bit magnitude comparator, enable		open-collector	20	SN74LS689
74x690	1	4-bit decimal counter/latch/multiplexer, asynchronous clear		三态逻辑	20	SN74LS690
74x691	1	4-bit binary counter/latch/multiplexer, asynchronous clear		三态逻辑	20	SN74LS691
74x692	1	4-bit decimal counter/latch/multiplexer, synchronous clear		三态逻辑	20	SN74LS692
74x693	1	4-bit binary counter/latch/multiplexer, synchronous clear		三态逻辑	20	SN74LS693
74x694	1	4-bit decimal counter/latch/multiplexer, synchronous and asynchronous clears		三态逻辑	20	SN74ALS694
74x695	1	4-bit binary counter/latch/multiplexer, synchronous and asynchronous clears		三态逻辑	20	SN74ALS695
74x696	1	4-bit decimal counter/register/multiplexer, asynchronous clear		三态逻辑	20	SN74LS696
74x697	1	4-bit binary counter/register/multiplexer, asynchronous clear		三态逻辑	20	SN74LS697
74x698	1	4-bit decimal counter/register/multiplexer, synchronous clear		三态逻辑	20	SN74LS698
74x699	1	4-bit binary counter/register/multiplexer, synchronous clear		三态逻辑	20	SN74LS699
模板:TOC tab	片内门电路个数	描述	输入	输出	Pin数目	数据手册
74x700	1	8个 dRAM driver, inverting		三态逻辑	20	SN74S700
74x701	1	8-bit register/counter/comparator		三态逻辑	24	74F701
74x702	1	8-bit registered read-back transceiver		三态逻辑	24	74F702
74x705	1	arithmetic logic unit for digital signal processing applications		三态逻辑	(84)	74ACT705
74x707	1	8-bit TTL-ECL shift register			20	74F707
74x708	1	576-bit FIFO memory (64x9)		三态逻辑	28	74ACT708
74x710	1	8-bit single-supply TTL-ECL shift register			20	74F710
74x711	5	quint 2-to-1 multiplexers		三态逻辑	20	74F711
74x712	5	quint 3-to-1 multiplexers			24	74F712
74x715	1	programmable video sync generator			20	74ACT715
74x716	1	programmable decade counter			16	SN74LS716
74x718	1	programmable binary counter			16	SN74LS718
74x723	1	576-bit FIFO memory (64x9)		三态逻辑	28	74ACT723
74x724	1	voltage-controlled multivibrator	analog		8	SN74LS724
74x725	1	4608-bit FIFO memory (512x9)		三态逻辑	28	74ACT725
74x730	1	8个 dRAM driver, inverting		三态逻辑	20	SN74S730
74x731	1	8个 dRAM driver, non-inverting		三态逻辑	20	SN74S731
74x732	1	4-bit 3-bus multiplexer, inverting		三态逻辑	20	74F732
74x733	1	4-bit 3-bus multiplexer, non-inverting		三态逻辑	20	74F733
74x734	1	8个 dRAM driver, non-inverting		三态逻辑	20	SN74S734
74x740	2	2个 4-bit line driver, inverting		三态逻辑	20	SN74S740
74x741	2	2个 4-bit line driver, non-inverting, complementary enable inputs		三态逻辑	20	SN74S741
74x742	1	8个 line driver, inverting		open-collector	20	SN74ALS742<ref name=ttltb3>模板:Cite book</ref>模板:Rp <ref name=catalogo>{{ if: {{#if: http://www.reniemarquet.com/kicad/libs/o_ttl.pdf \| {{#if: Catálogo de Componentes \|1}}}}	載入template:cite web時發生錯誤：網址（url）和標題（title）欄位為必填。 }}{{ if:	{{#if: \|1}}}}	載入template:cite web時發生錯誤：封存頁網址（archiveurl）和封存（archivedate）必須同時填寫或同時留空。 }} }}{{#if:	{{#if:	[[{{{authorlink}}}\|{{#if:	·{{{first}}} }}	{{{author}}} }}]]	{{#if:	·{{{first}}} }}	{{{author}}} }} }} }}{{#if:	； {{{coauthors}}} }} }}{{#if: \| {{#if: 2006-01-20	（2006-01-20）	{{#if:	{{#if:	（{{{year}}}{{{month}}}）	（{{{year}}}） }} }}

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}}</ref>模板:Rp |- 模板:Anchor | 74x743 | 1 | 8个 line driver, non-inverting | | open-collector | 20 | SN74ALS743<ref name=ttltb3/>模板:Rp <ref name=catalogo/>模板:Rp |- 模板:Anchor | 74x744 | 2 | 2个 4-bit line driver, non-inverting | | 三态逻辑 | 20 | SN74S744 |- 模板:Anchor | 74x746 | 1 | 8个 buffer / line driver, inverting | 20 kΩ pull-up | 三态逻辑 | 20 | SN74ALS746 |- 模板:Anchor | 74x747 | 1 | 8个 buffer / line driver, non-inverting | 20 kΩ pull-up | 三态逻辑 | 20 | SN74ALS747 |- 模板:Anchor | 74x748 | 1 | 8 to 3-line priority encoder (glitch-less) | | | 16 | SN74LS748 |- 模板:Anchor | 74x756 | 1 | 8个 buffer/line driver, inverting outputs | | open-collector | 20 | SN74AS756 |- 模板:Anchor | 74x757 | 1 | 8个 buffer/line driver, non-inverting outputs, complementary enable inputs | | open-collector | 20 | SN74AS757 |- 模板:Anchor | 74x758 | 1 | quadruple bus transceivers, inverting outputs | | open-collector | 14 | SN74AS758 |- 模板:Anchor | 74x759 | 1 | quadruple bus transceivers, non-inverting outputs | | open-collector | 14 | SN74AS759 |- 模板:Anchor | 74x760 | 1 | 8个 buffer/line driver, non-inverting outputs | | open-collector | 20 | SN74ALS760 |- 模板:Anchor | 74x762 | 1 | 8个 buffer/line driver, inverting and non-inverting outputs | | open-collector | 20 | SN74ALS762 |- 模板:Anchor | 74x763 | 1 | 8个 buffer/line driver, inverting outputs, complementary enable inputs | | open-collector | 20 | SN74ALS763 |- 模板:Anchor | 74x764 | 1 | 2个-port dRAM controller | | | 40 | 74F764 |- 模板:Anchor | 74x765 | 1 | 2个-port dRAM controller with address latch | | | 40 | 74F765 |- 模板:Anchor | 74x776 | 1 | 8-bit latched transceiver for FutureBus | | 三态逻辑 and open-collector | 28 | SN74F776 |- 模板:Anchor | 74x777 | 3 | 3个 latched transceiver | | 三态逻辑 and open-collector | 20 | 74F777 |- 模板:Anchor | 74x779 | 1 | 8-bit bidirectional binary counter | | 三态逻辑 | 16 | MC74F779 |- 模板:Anchor | 74x783 | 1 | synchronous address multiplexer for display systems | | | 40 | SN74LS783 |- 模板:Anchor | 74x784 | 1 | 8-bit serial/parallel multiplier with adder/subtractor | | | 20 | 74F784 |- 模板:Anchor | 74x785 | 1 | synchronous address multiplexer for display systems with 256-column refresh | | | 40 | SN74LS785 |- 模板:Anchor | 74x786 | 1 | 4输入 asynchronous bus arbiter | | | 16 | 74F786 |- 模板:Anchor | 74x790 | 1 | error detection and correction (EDAC) | | 三态逻辑 | 48 | SN74ALS790 |- 模板:Anchor | 74x793 | 1 | 8-bit latch, readback | | | 20 | SN74LS793 |- 模板:Anchor | 74x794 | 1 | 8-bit register, readback | | | 20 | SN74LS794 |- 模板:Anchor | 74x795 | 1 | 8个 buffer, non-inverting, common enable | | 三态逻辑 | 20 | SN74LS795 |- 模板:Anchor | 74x796 | 1 | 8个 buffer, inverting, common enable | | 三态逻辑 | 20 | SN74LS796 |- 模板:Anchor | 74x797 | 1 | 8个 buffer, non-inverting, enable for 4 buffers each | | 三态逻辑 | 20 | SN74LS797 |- 模板:Anchor | 74x798 | 1 | 8个 buffer, inverting, enable for 4 buffers each | | 三态逻辑 | 20 | SN74LS798 |- ! 模板:TOC tab ! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |- 模板:Anchor | 74x800 | 3 | 3个 4输入 AND/NAND drivers | | driver | 20 | SN74AS800 |- 模板:Anchor | 74x802 | 3 | 3个 4输入 OR/NOR drivers | | driver | 20 | SN74AS802 |- 模板:Anchor | 74x803 | 4 | 4个 D flip flops with matched propagation delays | | | 14 | MC74F803 |- 模板:Anchor | 74x804 | 6 | 6个 2输入 NAND drivers | | driver | 20 | SN74ALS804A |- 模板:Anchor | 74x805 | 6 | 6个 2输入 NOR drivers | | driver | 20 | SN74ALS805A |- 模板:Anchor | 74x807 | 1 | 1-to-10 clock driver | | driver | 20 | IDT74FCT807 |- 模板:Anchor | 74x808 | 6 | 6个 2输入 AND drivers | | driver | 20 | SN74AS808B |- 模板:Anchor | 74x810 | 4 | 4个 2输入 XNOR异或非门 | | | 14 | SN74ALS810 |- 模板:Anchor | 74x811 | 4 | 4个 2输入 XNOR异或非门 | | open-collector | 14 | DM74ALS811 |- 模板:Anchor | 74x818 | 1 | 8-bit diagnostic register | | 三态逻辑 | 24 | 74ACT818 |- 模板:Anchor | 74x819 | 1 | 8-bit diagnostic / pipeline register | | 三态逻辑 | 24 | SN74ALS819 |- 模板:Anchor | 74x821 | 1 | 10-bit bus interface flip-flop | | 三态逻辑 | 24 | SN74AS821A |- 模板:Anchor | 74x822 | 1 | 10-bit bus interface flip-flop, inverting inputs | | 三态逻辑 | 24 | SN74AS822 |- 模板:Anchor | 74x823 | 1 | 9-bit D-type flip-flops, clear and clock enable inputs | | 三态逻辑 | 24 | SN74AS823A |- 模板:Anchor | 74x824 | 1 | 9-bit D-type flip-flops, clear and clock enable inputs, inverting inputs | | 三态逻辑 | 24 | SN74AS824 |- 模板:Anchor | 74x825 | 1 | 8-bit D-type flip-flop, clear and clock enable inputs | | 三态逻辑 | 24 | SN74AS825A |- 模板:Anchor | 74x826 | 1 | 8-bit D-type flip-flop, clear and clock enable inputs, inverting inputs | | 三态逻辑 | 24 | SN74AS826 |- 模板:Anchor | 74x827 | 1 | 10-bit buffer, non-inverting | | 三态逻辑 | 24 | MC74F827 |- 模板:Anchor | 74x828 | 1 | 10-bit buffer, inverting | | 三态逻辑 | 24 | MC74F828 |- 模板:Anchor | 74x832 | 6 | 6个 2输入 OR drivers | | driver | 20 | SN74ALS832A |- 模板:Anchor | 74x833 | 1 | 8-bit to 9-bit bus transceiver with parity register, non-inverting | | 三态逻辑 | 24 | SN74ABT833 |- 模板:Anchor | 74x834 | 1 | 8-bit to 9-bit bus transceiver with parity register, inverting | | 三态逻辑 | 24 | IDT74FCT834 |- 模板:Anchor | 74x835 | 1 | 8-bit shift register with 2:1 input multiplexers, one input latched, serial output | | | 24 | 74F835 |- 模板:Anchor | 74x839 | 1 | field-programmable logic array 14x32x6 | | 三态逻辑 | 24 | SN74PL839 |- 模板:Anchor | 74x840 | 1 | field-programmable logic array 14x32x6 | | open-collector | 24 | SN74PL840 |- 模板:Anchor | 74x841 | 1 | 10-bit D-type flip-flop | | 三态逻辑 | 24 | SN74ALS841 |- 模板:Anchor | 74x842 | 1 | 10-bit D-type flip-flop, inverting inputs | | 三态逻辑 | 24 | SN74ALS842 |- 模板:Anchor | 74x843 | 1 | 9-bit D flip-flops, clear and set inputs | | 三态逻辑 | 24 | SN74ALS843 |- 模板:Anchor | 74x844 | 1 | 9-bit D flip-flops, clear and set inputs, inverting inputs | | 三态逻辑 | 24 | SN74ALS844 |- 模板:Anchor | 74x845 | 1 | 8-bit D flip-flops, clear and set inputs | | 三态逻辑 | 24 | SN74ALS845 |- 模板:Anchor | 74x846 | 1 | 8-bit D flip-flops, clear and set inputs, inverting inputs | | 三态逻辑 | 24 | SN74ALS846 |- 模板:Anchor | 74x848 | 1 | 8 to 3-line priority encoder (glitch-less) | | 三态逻辑 | 16 | SN74LS848 |- 模板:Anchor | 74x850 | 1 | 1 of 16 data selector/multiplexer, clocked select | | 三态逻辑 | 28 | SN74AS850 |- 模板:Anchor | 74x851 | 1 | 1 of 16 data selector/multiplexer | | 三态逻辑 | 28 | SN74AS851 |- 模板:Anchor | 74x852 | 1 | 8-bit universal transceiver port controller | | 三态逻辑 | 24 | SN74AS852 |- 模板:Anchor | 74x853 | 1 | 8-bit to 9-bit bus transceiver with parity latch, non-inverting | | 三态逻辑 | 24 | SN74ABT853 |- 模板:Anchor | 74x854 | 1 | 8-bit to 9-bit bus transceiver with parity latch, inverting | | 三态逻辑 | 24 | IDT74FCT854 |- 模板:Anchor | 74x856 | 1 | 8-bit universal transceiver port controller | | 三态逻辑 | 24 | SN74AS856 |- 模板:Anchor | 74x857 | 6 | 6个 2-line to 1-line multiplexer | | 三态逻辑 | 24 | SN74ALS857 |- 模板:Anchor | 74x861 | 1 | 10-bit bus transceiver, non-inverting | | 三态逻辑 | 24 | SN74ABT861 |- 模板:Anchor | 74x862 | 1 | 10-bit bus transceiver, inverting | | 三态逻辑 | 24 | SN74ABT862 |- 模板:Anchor | 74x863 | 1 | 9-bit bus transceiver, non-inverting | | 三态逻辑 | 24 | SN74ABT863 |- 模板:Anchor | 74x864 | 1 | 9-bit bus transceiver, inverting | | 三态逻辑 | 24 | 74F864 |- 模板:Anchor | 74x866 | 1 | 8-bit magnitude comparator with latches | | | 24 | SN74AS866 |- 模板:Anchor | 74x867 | 1 | synchronous 8-bit up/down counter, asynchronous clear | | | 24 | SN74ALS867A |- 模板:Anchor | 74x869 | 1 | synchronous 8-bit up/down counter, synchronous clear | | | 24 | SN74ALS869 |- 模板:Anchor | 74x870 | 1 | 2个 16x4 register files | | | 24 | SN74AS870 |- 模板:Anchor | 74x871 | 1 | 2个 16x4 register files | | | 28 | SN74AS871 |- 模板:Anchor | 74x873 | 2 | 2个 4-bit transparent latch with clear | | 三态逻辑 | 24 | SN74ALS873B |- 模板:Anchor | 74x874 | 2 | 2个 4-bit edge-triggered D flip-flops with clear | | 三态逻辑 | 24 | SN74ALS874 |- 模板:Anchor | 74x876 | 2 | 2个 4-bit edge-triggered D flip-flops with set, inverting outputs | | 三态逻辑 | 24 | SN74ALS876 |- 模板:Anchor | 74x877 | 1 | 8-bit universal transceiver port controller | | 三态逻辑 | 24 | SN74AS877 |- 模板:Anchor | 74x878 | 2 | 2个 4-bit D-type flip-flop, synchronous clear, non-inverting outputs | | 三态逻辑 | 24 | SN74ALS878 |- 模板:Anchor | 74x879 | 2 | 2个 4-bit D-type flip-flop, synchronous clear, inverting outputs | | 三态逻辑 | 24 | SN74ALS879 |- 模板:Anchor | 74x880 | 2 | 2个 4-bit transparent latch with clear, inverting outputs | | 三态逻辑 | 24 | SN74ALS880 |- 模板:Anchor | 74x881 | 1 | 4-bit arithmetic logic unit | | | 24 | SN74AS881A |- 模板:Anchor | 74x882 | 1 | 32-bit lookahead carry generator | | | 24 | SN74AS882 |- 模板:Anchor | 74x885 | 1 | 8-bit magnitude comparator | | | 24 | SN74AS885 |- 模板:Anchor | 74x887 | 1 | 8-bit processor element (non-cascadable version of 74x888) | | | (68) | SN74AS887 |- 模板:Anchor | 模板:Anchor74x888 | 1 | 8-bit processor slice | | | 64 | SN74AS888 |- 模板:Anchor | 74x889 | 1 | 8-bit processor slice | | | (68) | SN74AS889 |- 模板:Anchor | 74x890 | 1 | microoperation sequencer | | | 64 | SN74AS890 |- 模板:Anchor | 74x891 | 1 | microoperation sequencer | | | (68) | SN74AS891 |- 模板:Anchor | 74x895 | 1 | 8-bit memory address generator | | | (68) | SN74AS895 |- 模板:Anchor | 74x897 | 1 | 16-bit parallel/serial barrel shifter | | | (68) | SN74AS897A |- 模板:Anchor | 74x899 | 1 | 9-bit latchable transceiver with parity generator / checker | | 三态逻辑 | (28) | 74AC899 |- ! 模板:TOC tab ! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |- 模板:Anchor | 74x900 | 4 | 4个 2输入 NAND与非门 | | driver | 14 | SN74ALS900 |- 模板:Anchor | 74x901 | 6 | 6个 inverting TTL buffer | | | 14 | MM74C901 |- 模板:Anchor | 74C902 | 6 | 6个 non-inverting TTL buffer | | | 14 | MM74C902 |- | 74ALS902 | 4 | 4个 2输入 NOR 或非门 | | driver | 14 | SN74ALS902 |- 模板:Anchor | 74C903 | 6 | 6个 inverting PMOS buffer | | | 14 | MM74C903 |- | 74ALS903 | 4 | 4个 2输入 NAND与非门 | | open-collector driver | 14 | SN74ALS903 |- 模板:Anchor | 74x904 | 6 | 6个 non-inverting PMOS buffer | | | 14 | MM74C904 |- 模板:Anchor | 74x905 | 1 | 12-bit successive approximation register | | | 24 | MM74C905 |- 模板:Anchor | 74x906 | 6 | 6个 open drain n-channel buffers | | open-collector | 14 | MM74C906 |- 模板:Anchor | 74x907 | 6 | 6个 open drain p-channel buffers | | 模板:Unknown | 14 | MM74C907 |- 模板:Anchor | 74x908 | 2 | 2个 2输入 NAND 30 V / 250 mA relay driver | | 模板:Unknown | 8 | MM74C908 |- 模板:Anchor | 74x909 | 4 | 4个 voltage comparator | analog | open-collector | 14 | MM74C909 |- 模板:Anchor | 74x910 | 1 | 256-bit RAM (64x4) | | 三态逻辑 | 18 | MM74C910 |- 模板:Anchor | 74x911 | 1 | 4-digit expandable display controller | | 三态逻辑 | 28 | MM74C911 |- 模板:Anchor | 74x912 | 1 | 6-digit BCD display controller and driver | | 三态逻辑 | 28 | MM74C912 |- 模板:Anchor | 74x913 | 1 | 6-digit BCD display controller and driver, no decimal point | | | 24 | MM74C913 |- 模板:Anchor | 74x914 | 6 | 6个非门, extended input voltage | Schmitt trigger | | 14 | MM74C914 |- 模板:Anchor | 74x915 | 1 | 7-segment to BCD converter | | 三态逻辑 | 18 | MM74C915 |- 模板:Anchor | 74x917 | 1 | 6-digit 6个 display controller and driver | | 三态逻辑 | 28 | MM74C917 |- 模板:Anchor | 74x918 | 2 | 2个 2输入 NAND 30 V / 250 mA relay driver | | 模板:Unknown | 14 | MM74C918 |- 模板:Anchor | 74x920 | 1 | 1024-bit RAM (256x4), separate data inputs and outputs | | 三态逻辑 | 22 | MM74C920 |- 模板:Anchor | 74x921 | 1 | 1024-bit RAM (256x4) | | 三态逻辑 | 18 | MM74C921 |- 模板:Anchor | 74x922 | 1 | 16-key encoder | | 三态逻辑 | 18 | MM74C922 |- 模板:Anchor | 74x923 | 1 | 20-key encoder | | 三态逻辑 | 20 | MM74C923 |- 模板:Anchor | 74x925 | 1 | 4-digit counter/display driver | | | 16 | MM74C925 |- 模板:Anchor | 74x926 | 1 | 4-digit decade counter/display driver, carry out and latch (up to 9999) | | | 16 | MM74C926 |- 模板:Anchor | 74x927 | 1 | 4-digit timer counter/display driver (up to 9599, intended as time elapsed, i.e. 9:59.9 min) | | | 16 | MM74C927 |- 模板:Anchor | 74x928 | 1 | 4-digit counter/display driver (up to 1999) | | | 16 | MM74C928 |- 模板:Anchor | 74x929 | 1 | 1024-bit RAM (1024x1), single chip select | | 三态逻辑 | 16 | MM74C929 |- 模板:Anchor | 74x930 | 1 | 1024-bit RAM (1024x1), three chip selects | | 三态逻辑 | 18 | MM74C930 |- 模板:Anchor | 74x932 | 1 | phase comparator | | | 8 | MM74C932 |- 模板:Anchor | 74x933 | 1 | 7-bit address bus comparator | | | 20 | MM74C933 |- 模板:Anchor | 74934 | 1 | ADC similar to ADC0829, see corresponding NSC datasheet | | | | |- 模板:Anchor | 74x935 | 1 | ADC for 3.5-digit digital voltmeters, multiplexed 7-segment display outputs | analog | | 28 | MM74C935 |- 模板:Anchor | 74x936 | 1 | ADC for 3.75-digit digital voltmeters, multiplexed 7-segment display outputs | analog | | 模板:Unknown | MM74C936 |- 模板:Anchor | 74x937 | 1 | ADC for 3.5-digit digital voltmeters, multiplexed BCD outputs | analog | | 24 | MM74C937 |- 模板:Anchor | 74x938 | 1 | ADC for 3.75-digit digital voltmeters, multiplexed BCD outputs | analog | | 24 | MM74C938 |- 模板:Anchor | 74x940 | 1 | 8个 bus/line drivers/line receivers | Schmitt trigger | 三态逻辑 | 20 | DM74S940 |- 模板:Anchor | 74x941 | 1 | 8个 bus/line drivers/line receivers | Schmitt trigger | 三态逻辑 | 20 | DM74S941 |- 模板:Anchor | 74x942 | 1 | 300 baud Bell 103 modem (+/- 5 V supply) | | | 20 | MM74HC942 |- 模板:Anchor | 74x943 | 1 | 300 baud Bell 103 modem (single 5 V supply) | | | 20 | MM74HC943 |- 模板:Anchor | 74x945 | 1 | 4-digit up/down counter, decoder and LCD driver, output latch | | | 40 | MM74C945 |- 模板:Anchor | 74x946 | 1 | 4.5-digit counter, decoder and LCD driver, leading zero blanking | | | 40 | MM74C946 |- 模板:Anchor | 74x947 | 1 | 4-digit up/down counter, decoder and LCD driver, leading zero blanking | | | 40 | MM74C947 |- 模板:Anchor | 74x948 | 1 | 8-bit ADC with 16-channel analog multiplexer | analog | 三态逻辑 | 40 | MM74C948 |- 模板:Anchor | 74x949 | 1 | 8-bit ADC with 8-channel analog multiplexer | analog | 三态逻辑 | 28 | MM74C949 |- 模板:Anchor | 74x950 | 1 | 8-bit ADC with 8-channel analog multiplexer and sample and hold | analog | 三态逻辑 | 28 | MM74C950 |- 模板:Anchor | 74x952 | 1 | 2个 rank 8-bit shift register, synchronous clear | | 三态逻辑 | 18 | DM74LS952 |- 模板:Anchor | 74C956 | 1 | 4-digit, 17-segment alpha-numeric LED display driver with memory and decoder | | | 40 | MM74C956 |- | 74BCT956 | 1 | 8个 bus transceiver and latch | | 三态逻辑 | 24 | SN74BCT956 |- 模板:Anchor | 74x962 | 1 | 2个 rank 8-bit shift register, register exchange mode | | 三态逻辑 | 18 | DM74LS962 |- 模板:Anchor | 74x963 | 1 | 2个 rank 8-bit shift register, synchronous clear | | 三态逻辑 | 20 | SN74ALS963 |- 模板:Anchor | 74x964 | 1 | 2个 rank 8-bit shift register, synchronous and asynchronous clear | | 三态逻辑 | 20 | SN74ALS964 |- 模板:Anchor | 74x968 | 1 | controller/driver for 16k/64k/256k/1M dRAM | | | 52 | 74F968 |- 模板:Anchor | 74x978 | 1 | 8个 flip-flop with serial scanner | | | 24 | 74F978 |- 模板:Anchor | 74x979 | 1 | 9-bit registered transceiver with parity generator/checker for FutureBus | | 三态逻辑 and open-collector | (48) | SN74BCT979 |- 模板:Anchor | 74x989 | 1 | 64-bit RAM (64x4), inverting output | | 三态逻辑 | 16 | MM74C989 |- 模板:Anchor | 74x990 | 1 | 8-bit D-type transparent read-back latch, non-inverting | | 三态逻辑 | 20 | SN74ALS990 |- 模板:Anchor | 74x991 | 1 | 8-bit D-type transparent read-back latch, inverting | | 三态逻辑 | 20 | SN74ALS991 |- 模板:Anchor | 74x992 | 1 | 9-bit D-type transparent read-back latch, non-inverting | | 三态逻辑 | 24 | SN74ALS992 |- 模板:Anchor | 74x993 | 1 | 9-bit D-type transparent read-back latch, inverting | | 三态逻辑 | 24 | SN74ALS993 |- 模板:Anchor | 74x994 | 1 | 10-bit D-type transparent read-back latch, non-inverting | | 三态逻辑 | 24 | SN74ALS994 |- 模板:Anchor | 74x995 | 1 | 10-bit D-type transparent read-back latch, inverting | | 三态逻辑 | 24 | SN74ALS995 |- 模板:Anchor | 74x996 | 1 | 8-bit D-type edge-triggered read-back latch | | 三态逻辑 | 24 | SN74ALS996 |- ! 模板:TOC tab ! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |- | 74x1000 | 4 | 4个 2输入 NAND与非门 | | driver | 14 | SN74AS1000A |- | 74x1002 | 4 | 4个 2输入 NOR 或非门 | | driver | 14 | SN74ALS1002A |- | 74x1003 | 4 | 4个 2输入 NAND与非门 | | open-collector driver | 14 | SN74ALS1003A |- | 74x1004 | 6 | 6个 inverting buffer | | driver | 14 | SN74ALS1004 |- | 74x1005 | 6 | 6个 inverting buffer | | open-collector driver | 14 | SN74ALS1005 |- | 74x1008 | 4 | 4个 2输入 AND与门 | | driver | 14 | SN74AS1008A |- | 74ALS1010 | 3 | 3个 3输入 NAND与非门 | | driver | 14 | SN74ALS1010A |- | 74AC1010,
74ACT1010 | 1 | 16x16-bit multiplier/accumulator | | 三态逻辑 | 64 | 74AC1010 |- | 74x1011 | 3 | 3个 3输入 AND与门 | | driver | 14 | SN74ALS1011A |- | 74F1016 | 16 | 16-bit Schottky diode R-C bus termination array | | 模板:Unknown | (20) | SN74F1016 |- | 74AC1016,
74ACT1016 | 1 | 16x16-bit multiplier | | 三态逻辑 | 64 | 74AC1016 |- | 74x1017 | 1 | 16x16-bit parallel multiplier | | 三态逻辑 | 64 | 74AC1017 |- | 74x1018 | 18 | 18-bit Schottky diode R-C bus termination array | | 模板:Unknown | (24) | SN74F1018 |- | 74x1020 | 2 | 2个 4输入 NAND与非门 | | driver | 14 | SN74ALS1020A |- | 74x1032 | 4 | 4个 2输入 OR或门 | | driver | 14 | SN74AS1032A |- | 74x1034 | 6 | 6个 non-inverting buffer | | driver | 14 | SN74ALS1034 |- | 74x1035 | 6 | 6个 non-inverting buffer | | open-collector driver | 14 | SN74ALS1035 |- | 74x1036 | 4 | 4个 2输入 NOR 或非门 | | driver | 14 | SN74ALS1036 |- | 74x1050 | 12 | 12-bit Schottky diode bus termination array, clamp to GND | | 模板:Unknown | 16 | SN74S1050 |- | 74x1051 | 12 | 12-bit Schottky diode bus termination array, clamp to GND/V_CC | | 模板:Unknown | 16 | SN74S1051 |- | 74x1052 | 16 | 16-bit Schottky diode bus termination array, clamp to GND | | 模板:Unknown | 20 | SN74S1052 |- | 74x1053 | 16 | 16-bit Schottky diode bus termination array, clamp to GND/V_CC | | 模板:Unknown | 20 | SN74S1053 |- | 74x1056 | 8 | 8-bit Schottky diode bus termination array, clamp to GND | | 模板:Unknown | (16) | SN74F1056 |- | 74x1071 | 10 | 10-bit bus termination array with bus-hold function | | | (14) | SN74ACT1071 |- | 74x1073 | 16 | 16-bit bus termination array with bus-hold function | | | (20) | SN74ACT1073 |- | 74x1074 | 2 | 2个 D negative edge triggered flip-flop, asynchronous preset and clear | | | 14 | 74FR1074 |- | 74x1181 | 1 | 4-bit arithmetic logic unit | | | 24 | SN74AS1181 |- | 74x1240 | 1 | 8个 buffer / line driver, inverting (lower-power version of 74x240) | | 三态逻辑 | 20 | SN74ALS1240 |- | 74x1241 | 1 | 8个 buffer / line driver, non-inverting (lower-power version of 74x241) | | 三态逻辑 | 20 | SN74ALS1241 |- | 74x1242 | 1 | 4个 bus transceiver, inverting (lower-power version of 74x242) | | 三态逻辑 | 14 | SN74ALS1242 |- | 74x1243 | 1 | 4个 bus transceiver, non-inverting (lower-power version of 74x243) | | 三态逻辑 | 14 | SN74ALS1243 |- | 74x1244 | 1 | 8个 buffer / driver, non-inverting (lower-power version of 74x244) | | 三态逻辑 | 20 | SN74ALS1244 |- | 74x1245 | 1 | 8个 bus transceiver (lower-power version of 74x245) | | 三态逻辑 | 20 | SN74ALS1245A |- | 74x1280 | 1 | 9-bit parity generator/checker with registered outputs | | 三态逻辑 | 20 | QS74FCT1280 |- | 74x1284 | 1 | parallel printer interface transceiver / buffer (IEEE 1284) | | | 20 | 74HCT1284 |- | 74x1403 | 1 | 8-bit bus receiver plus 4-bit bus driver | Schmitt trigger | 三态逻辑 | (32) | 74LVT1403 |- | 74x1404 | 1 | oscillator driver | Schmitt trigger | | (8) | SN74LVC1404 |- | 74x1604 | 1 | 2个 8-bit transparent latch with output multiplexer | | | 28 | 74F1604 |- | 74x1616 | 1 | 16x16-bit multimode multiplier | | 三态逻辑 | 64 | SN74ALS1616 |- | 74x1620 | 1 | 8个 bus transceiver, inverting | | 三态逻辑 | 20 | SN74ALS1620 |- | 74x1621 | 1 | 8个 bus transceiver, non-inverting | | open-collector | 20 | SN74ALS1621 |- | 74x1622 | 1 | 8个 bus transceiver, inverting | | open-collector | 20 | SN74ALS1622 |- | 74x1623 | 1 | 8个 bus transceiver, non-inverting | | 三态逻辑 | 20 | SN74ALS1623 |- | 74x1631 | 1 | 4个 bus driver with complementary outputs | | 三态逻辑 | 16 | SN74ALS1631<ref name=ttltb3/>模板:Rp |- | 74x1638 | 1 | 8个 bus transceiver, inverting (lower-power version of 74x638) | | 三态逻辑 and open-collector | 20 | SN74ALS1638 |- | 74x1639 | 1 | 8个 bus transceiver, non-inverting (lower-power version of 74x639) | | 三态逻辑 and open-collector | 20 | SN74ALS1639 |- | 74x1640 | 1 | 8个 bus transceiver, inverting (lower-power version of 74x640) | | 三态逻辑 | 20 | SN74ALS1640A |- | 74x1641 | 1 | 8个 bus transceiver, non-inverting (lower-power version of 74x641) | | open-collector | 20 | SN74ALS641 |- | 74x1642 | 1 | 8个 bus transceiver, inverting (lower-power version of 74x642) | | open-collector | 20 | SN74ALS642 |- | 74x1643 | 1 | 8个 bus transceiver, inverting and non-inverting (lower-power version of 74x643) | | 三态逻辑 | 20 | SN74ALS643 |- | 74x1644 | 1 | 8个 bus transceiver, inverting and non-inverting (lower-power version of 74x644) | | open-collector | 20 | SN74ALS644 |- | 74x1645 | 1 | 8个 bus transceiver, non-inverting (lower-power version of 74x645) | | 三态逻辑 | 20 | SN74ALS1645A |- | 74x1650 | 2 | 2个 9-bit Futurebus universal storage transceiver with split TTL I/O | | 三态逻辑 and open-collector | (100) | SN74FB1650 |- | 74x1651 | 2 | 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split TTL I/O | | 三态逻辑 and open-collector | (100) | SN74FB1651 |- | 74x1653 | 2 | 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split 3.3V TTL I/O | | 三态逻辑 and open-collector | (100) | SN74FB1653 |- | 74x1665 | 2 | 2个 8-bit GTL universal storage transceivers with live insertion | | 三态逻辑 and open-collector | (64) | SN74GTL1655 |- | 74x1760 | 1 | 10-bit 4-way latched address multiplexer | | 三态逻辑 | 64 | 74F1760 |- | 74x1761 | 1 | dRAM and interrupt vector controller | | | 48 | 74F1761 |- | 74x1762 | 1 | dRAM address controller | | | 40 | 74F1762 |- | 74x1763 | 1 | 1个-port dRAM controller | | | 48 | 74F1763 |- | 74x1764 | 1 | 2个-port dRAM controller | | | 48 | 74F1764 |- | 74x1765 | 1 | 2个-port dRAM controller with address latch | | | 48 | 74F1765 |- | 74x1766 | 1 | burst mode dRAM controller | | | 48 | 74F1766 |- | 74x1779 | 1 | 8-bit bidirectional binary counter | | 三态逻辑 | 16 | 74F1779 |- | 74x1801 | 1 | FM, MFM, and DM encoder / decoder, data rates up to 10 MHz | | | 24 | 74LS1801 |- | 74x1802 | 1 | SerDes with ECC and CRC, data rates up to 10 MHz | | 三态逻辑 | 48 | 74LS1802 |- | 74x1803 | 1 | 4个 clock driver | | | 14 | MC74F1803 |- | 74x1804 | 6 | 6个 2输入 NAND | | driver | 20 | DM74AS1804 |- | 74x1805 | 6 | 6个 2输入 NOR | | driver | 20 | DM74AS1805 |- | 74x1808 | 6 | 6个 2输入 AND | | driver | 20 | DM74AS1808 |- | 74x1811 | 1 | FM, MFM, and DM encoder / decoder, data rates up to 20 MHz | | | 24 | 74LS1811 |- | 74x1812 | 1 | SerDes with ECC and CRC, data rates up to 30 MHz | | 三态逻辑 | 48 | 74LS1812 |- | 74x1821 | 1 | 10-bit bus interface flip-flops | | 三态逻辑 | 24 | SN74AS1821 |- | 74x1823 | 1 | 9-bit bus interface flip-flops with clear | | 三态逻辑 | 24 | SN74AS1823 |- | 74x1832 | 6 | 6个 2输入 OR | | driver | 20 | DM74ALS1832 |- | 74x1841 | 1 | 10-bit bus interface transparent latches | | 三态逻辑 | 24 | SN74AS1841 |- | 74x1843 | 1 | 9-bit bus interface transparent latches with clear | | 三态逻辑 | 24 | SN74AS1843 |- ! 模板:TOC tab ! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |- | 74x2000 | 1 | direction discriminator with microprocessor interface | | 三态逻辑 | 28 | SN74LS2000 |- | 74x2003 | 1 | 8-bit level translator | | 模板:Unknown | (20) | SN74GTL2003 |- | 74x2006 | 1 | 13-bit GTL to 3.3V TTL level translator | | open-collector | (28) | SN74GTL2006 |- | 74x2007 | 1 | 12-bit GTL to 3.3V TTL level translator | | open-collector | (28) | SN74GTL2007 |- | 74x2010 | 1 | 10-bit level translator | | 模板:Unknown | (24) | SN74GTL2010 |- | 74x2014 | 1 | 4-bit GTL to TTL transceiver | | 三态逻辑 and open-collector | (14) | SN74GTL2014 |- | 74x2031 | 1 | 9-bit Futurebus address/data transceiver | | 三态逻辑 and open-collector | (48) | SN74FB2031 |- | 74x2032 | 1 | 9-bit Futurebus competition transceiver | | 三态逻辑 and open-collector | (48) | SN74FB2032 |- | 74x2033 | 1 | 8-bit Futurebus registered transceiver with split TTL I/O | | 三态逻辑 and open-collector | (52) | SN74FB2033 |- | 74x2040 | 1 | 8-bit Futurebus transceiver with split TTL I/O | | 三态逻辑 and open-collector | (48) | SN74FB2040 |- | 74x2041 | 1 | 7-bit Futurebus transceiver with split TTL I/O | | 三态逻辑 and open-collector | (52) | SN74FB2041 |- | 74x2107 | 1 | 12-bit GTL to 3.3V TTL level translator | | open-collector | (28) | SN74GTL2107 |- | 74x2125 | 4 | 4个 bus buffer | | 三态逻辑, 25 Ω series resistor | (14) | TC74VCX2125 |- | 74x2140 | 1 | 8k x 18 cache data RAM | | 三态逻辑 | (52) | SN74ACT2140A |- | 74x2150 | 1 | 512 x 8 cache address comparator | | | 24 | SN74ACT2150A |- | 74ACT2151 | 1 | 1k x 11 cache address comparator | | | 28 | SN74ACT2151 |- | 74FCT2151 | 1 | 8-line to 1-line multiplexer | | 25 Ω series resistor | (16) | CD74FCT2151 |- | 74x2152 | 1 | 2k x 8 cache address comparator | | | 28 | SN74ACT2152A |- | 74ACT2153 | 1 | 1k x 11 cache address comparator | | open-collector | 28 | SN74ACT2153 |- | 74FCT2153 | 2 | 2个 4-line to 1-line multiplexer | | 25 Ω series resistor | (16) | CD74FCT2153 |- | 74x2154 | 1 | 2k x 8 cache address comparator | | open-collector | 28 | SN74ACT2154A |- | 74x2155 | 1 | 2k x 8 burst cache address comparator | | 三态逻辑 | (44) | SN74ACT2155 |- | 74x2156 | 1 | 16k x 4 burst cache address comparator | | 三态逻辑 | (44) | SN74ACT2156 |- | 74ACT2157 | 1 | 2k x 16 cache address comparator | | 三态逻辑 | (44) | SN74ACT2157 |- | 74FCT2157 | 4 | 4个 2-line to 1-line multiplexer | | 25 Ω series resistor | (16) | CD74FCT2157 |- | 74x2158 | 1 | 8k x 9 cache address comparator | | 三态逻辑 | (44) | SN74ACT2158 |- | 74x2159 | 1 | 8k x 9 cache address comparator | | 三态逻辑 | (44) | SN74ACT2159 |- | 74x2160 | 1 | 8k x 4 2-way cache address comparator | | 三态逻辑 | (32) | SN74ACT2160 |- | 74x2161 | 1 | synchronous presettable 4-bit binary counter, asynchronous clear | | 25 Ω series resistor | 16 | QS74FCT2161T |- | 74ACT2163,
74BCT2163 | 1 | 16k x 5 cache address comparator | | 三态逻辑 | (32) | SN74ACT2163 |- | 74FCT2163 | 1 | synchronous presettable 4-bit binary counter, synchronous clear | | 25 Ω series resistor | 16 | QS74FCT2163T |- | 74x2164 | 1 | 16k x 5 cache address comparator | | 三态逻辑 | (32) | SN74ACT2164 |- | 74x2166 | 1 | 16k x 5 cache address comparator with input latches | | 三态逻辑 | (32) | SN74BCT2166 |- | 74x2191 | 1 | synchronous presettable 4-bit binary up/down counter, common clock | | 25 Ω series resistor | 16 | QS74FCT2191T |- | 74x2193 | 1 | synchronous presettable 4-bit binary counter, separate up/down clocks | | 25 Ω series resistor | 16 | QS74FCT2193T |- | 74x2226 | 2 | 2个 64-bit FIFO memories (64x1) | | | (24) | SN74ACT2226 |- | 74x2227 | 2 | 2个 64-bit FIFO memories (64x1) | | 三态逻辑 | (28) | SN74ACT2227 |- | 74x2228 | 2 | 2个 256-bit FIFO memories (256x1) | | | (24) | SN74ACT2228 |- | 74x2229 | 2 | 2个 256-bit FIFO memories (256x1) | | 三态逻辑 | (28) | SN74ACT2229 |- | 74x2232 | 1 | 512-bit FIFO memory (64x8) | | 三态逻辑 | 24 | SN74ALS2232A |- | 74x2233 | 1 | 576-bit FIFO memory (64x9) | | 三态逻辑 | 28 | SN74ALS2233A |- | 74x2235 | 1 | 18432-bit bidirectional FIFO memory (2x1024x9) | | 三态逻辑 | (44) | SN74ACT2235 |- | 74x2236 | 1 | 18432-bit bidirectional FIFO memory (2x1024x9) | | 三态逻辑 | (44) | SN74ACT2236 |- | 74x2238 | 1 | 576-bit bidirectional FIFO memory (2x32x9) | | 三态逻辑 | 40 | SN74ALS2238 |- | 74x2240 | 2 | 2个 4-bit bidirectional buffer / line driver, inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74BCT2240 |- | 74x2241 | 2 | 2个 4-bit bidirectional buffer / line driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74BCT2241 |- | 74x2242 | 1 | 4-bit bus transceiver, inverting | | 三态逻辑, 25 Ω series resistor | 14 | SN74ALS2242 |- | 74x2243 | 1 | 4-bit bus transceiver, non-inverting | | 三态逻辑, 25 Ω series resistor | (14) | 74F2243 |- | 74x2244 | 2 | 2个 4-bit buffer / line driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74BCT2244 |- | 74x2245 | 1 | 8个 bus transceiver | | 三态逻辑, 25 Ω series resistor | 20 | SN74ABT2245 |- | 74x2253 | 2 | 2个 4-line to 1-line multiplexer | | 三态逻辑, 25 Ω series resistor | (16) | CD74FCT2253 |- | 74x2257 | 4 | 4个 2-line to 1-line multiplexer | | 三态逻辑, 25 Ω series resistor | (16) | CD74FCT2257 |- | 74x2273 | 8 | 8个 D-type flip-flop with common clock and reset | | 25 Ω series resistor | (20) | CD74FCT2273 |- | 74x2299 | 1 | 8-bit universal shift register | | 三态逻辑, 25 Ω series resistor | 20 | QS74FCT2299T |- | 74x2323 | 2 | 2个 line receiver | 模板:Unknown | | (8) | SN74LS2323 |- | 74x2373 | 1 | 8-bit transparent latch | | 三态逻辑, 25 Ω series resistor | (20) | CD74FCT2373 |- | 74x2374 | 8 | 8个 D-type flip-flop with common clock | | 三态逻辑, 25 Ω series resistor | (20) | CD74FCT2374 |- | 74x2377 | 1 | 8-bit register with clock enable | | 25 Ω series resistor | 20 | QS74FCT2377T |- | 74x2400 | 2 | 2个 4-bit buffer, inverting | Schmitt trigger | 三态逻辑 | 20 | 74THC2400 |- | 74x2410 | 1 | 11-bit MOS memory driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 28 | SN74BCT2410 |- | 74x2411 | 1 | 11-bit MOS memory driver, inverting | | 三态逻辑, 25 Ω series resistor | 28 | SN74BCT2411 |- | 74x2414 | 2 | 2个 2-to-4 line decoder with supply voltage monitor | | | 20 | SN74BCT2414 |- | 74x2420 | 1 | 16-bit NuBus address/data transceiver and register | | 三态逻辑 | (68) | SN74BCT2420 |- | 74x2423 | 1 | 16-bit latched multiplexer/demultiplexer NuBus transceiver, inverting | | 三态逻辑 | (68) | SN74BCT2423 |- | 74x2424 | 1 | 16-bit latched multiplexer/demultiplexer NuBus transceiver, non-inverting | | 三态逻辑 | (68) | SN74BCT2424 |- | 74x2425 | 1 | Macintosh Coprocessor Platform NuBus address/data registered transceiver | | 三态逻辑 | (100) | SN74BCT2425 |- | 74x2440 | 1 | NuBus interface controller | | | (68) | SN74ACT2440 |- | 74x2441 | 1 | NuBus interface controller | | | (100) | SN74ACT2441 |- | 74x2442 | 1 | NuBus block slave address generator | | 三态逻辑 | (20) | SN74ALS2442 |- | 74x2509 | 1 | 9-output clock driver with PLL | | 三态逻辑 | (24) | HD74CDC2509 |- | 74x2510 | 1 | 10-output clock driver with PLL | | 三态逻辑 | (24) | HD74CDC2510 |- | 74x2525 | 1 | 8-output clock driver | | | 14 | 74AC2525 |- | 74x2526 | 1 | 8-output clock driver with input multiplexer | | | 16 | 74AC2526 |- | 74x2533 | 1 | 8-bit bus interface latch, inverting | | 三态逻辑, 25 Ω series resistor | 20 | QS74FCT2533T |- | 74x2534 | 1 | 8-bit bus interface register, inverting | | 三态逻辑, 25 Ω series resistor | 20 | QS74FCT2534T |- | 74x2540 | 1 | 8-bit buffer / line driver, inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74ALS2540 |- | 74x2541 | 1 | 8-bit buffer / line driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74ALS2541 |- | 74x2543 | 1 | 8-bit latched transceiver, non-inverting | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2543T |- | 74x2544 | 1 | 8-bit latched transceiver, inverting | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2544T |- | 74x2573 | 1 | 8-bit transparent latch | | 三态逻辑, 25 Ω series resistor | 20 | QS74FCT2573T |- | 74x2574 | 8 | 8个 D-type flip-flop with common clock | | 三态逻辑, 25 Ω series resistor | 20 | QS74FCT2574T |- | 74x2620 | 1 | 8个 bus transceiver / MOS driver, inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74AS2620 |- | 74x2623 | 1 | 8个 bus transceiver / MOS driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74AS2623 |- | 74x2640 | 1 | 8个 bus transceiver / MOS driver, inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74AS2640 |- | 74x2643 | 1 | 8个 bus transceiver, mix of inverting and non-inverting outputs | | 三态逻辑, 25 Ω series resistor | 20 | 74F2643 |- | 74x2645 | 1 | 8个 bus transceiver / MOS driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 20 | SN74AS2645 |- | 74x2646 | 1 | 8个 registered transceiver, non-inverting | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2646T |- | 74x2648 | 1 | 8个 registered transceiver, inverting | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2648T |- | 74x2651 | 1 | 8个 registered transceiver, inverting | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2651T |- | 74x2652 | 1 | 8个 registered transceiver, non-inverting | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2652T |- | 74S2708 | 1 | 8192-bit PROM (1024x8) | | 三态逻辑 | 24 | SN74S2708 |- | 74AC2708 | 1 | 576-bit FIFO memory (64x9) | | 三态逻辑 | 28 | 74AC2708 |- | 74x2725 | 1 | 4608-bit FIFO memory (512x9) | | | 28 | 74ACT2725 |- | 74x2726 | 1 | 4608-bit bidirectional FIFO memory (512x9) | | | 28 | 74ACT2726 |- | 74x2821 | 1 | 10-bit D-type flip-flop | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2821T |- | 74x2823 | 1 | 9-bit D-type flip-flop with clear | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2823T |- | 74x2825 | 1 | 8-bit D-type flip-flop with clear and clock enable | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2825T |- | 74x2827 | 1 | 10-bit buffer, non-inverting | | 三态逻辑, 25 Ω series resistor | 24 | SN74BCT2827A |- | 74x2828 | 1 | 10-bit buffer, inverting | | 三态逻辑, 25 Ω series resistor | 24 | SN74BCT2828A |- | 74x2833 | 1 | 8-bit bus transceiver with parity error flip-flop | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2833T |- | 74x2841 | 1 | 10-bit transparent latch | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2841T |- | 74x2843 | 1 | 9-bit transparent latch with asynchronous reset | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2843T |- | 74x2845 | 1 | 8-bit transparent latch with asynchronous reset and multiple output enable | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2845T |- | 74x2853 | 1 | 8-bit bus transceiver with parity error latch | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2853T |- | 74x2861 | 1 | 10-bit non-inverting bus transceiver | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2861T |- | 74x2862 | 1 | 10-bit inverting bus transceiver | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2862T |- | 74x2863 | 1 | 9-bit non-inverting bus transceiver with 2个 output enable | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2863T |- | 74x2864 | 1 | 9-bit inverting bus transceiver with 2个 output enable | | 三态逻辑, 25 Ω series resistor | 24 | QS74FCT2864T |- | 74x2952 | 1 | 8个 bus transceiver and register, non-inverting | | 三态逻辑 | 24 | SN74LVC2952A |- | 74x2953 | 1 | 8个 bus transceiver and register, inverting | | 三态逻辑 | 24 | 74F2953 |- | 74x2960模板:Anchor | 1 | error detection and correction (EDAC), equivalent to Am2960 | | 三态逻辑 | 48 | MC74F2960 |- | 74x2961 | 1 | 4-bit EDAC bus buffer, inverting, equivalent to Am2961 | | 三态逻辑 | 24 | MC74F2961A |- | 74x2962 | 1 | 4-bit EDAC bus buffer, non-inverting, equivalent to Am2962 | | 三态逻辑 | 24 | MC74F2962A |- | 74x2967 | 1 | controller/driver for 16k/64k/256k dRAM | | | 48 | SN74ALS2967 |- | 74x2968 | 1 | controller/driver for 16k/64k/256k dRAM | | | 48 | SN74ALS2968 |- | 74x2969 | 1 | memory timing controller for use with EDAC | | | 48 | MC74F2969 |- | 74x2970 | 1 | memory timing controller for use without EDAC | | | 24 | MC74F2970 |- ! 模板:TOC tab ! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |- | 74x3004 | 1 | selectable GTL voltage reference | | 模板:Unknown | (6) | SN74GTL3004 |- | 74x3037 | 4 | 4个 2输入 NAND与非门 | | driver 30 Ω | 16 | 74F3037 |- | 74x3038 | 4 | 4个 2输入 NAND与非门 | | open-collector driver 30 Ω | 16 | 74F3038 |- | 74x3040 | 2 | 2个 4输入 NAND与非门 | | driver 30 Ω | 16 | 74F3040 |- | 74x3125 | 4 | 4个 FET bus switch, output enable active low | | 模板:Unknown | (14) | SN74CBT3125 |- | 74x3126 | 4 | 4个 FET bus switch, output enable active high | | 模板:Unknown | (14) | SN74CBT3126 |- | 74FCT3244 | 2 | 2个 4-bit buffer / line driver | | 三态逻辑 | 20 | IDT74FCT3244 |- | 74CBT3244,
74FST3244 | 2 | 2个 4-bit FET bus switch | | 模板:Unknown | 20 | SN74CBT3244
IDT74FST3244 |- | 74FCT3245 | 1 | 8个 bidirectional transceiver | | 三态逻辑 | 20 | IDT74FCT3245 |- | 74CBT3245,
74FST3245 | 1 | 8个 FET bus switch | | 模板:Unknown | 20 | SN74CBT3245A
IDT74FST3245 |- | 74LVX3245 | 1 | 8个 bidirectional voltage-translating transceiver | | 三态逻辑 | (24) | 74LVX3245 |- | 74x3251 | 1 | 8-line to 1-line FET multiplexer / demultiplexer | | 模板:Unknown | (16) | SN74CBT3251 |- | 74x3253 | 2 | 2个 4-line to 1-line FET multiplexer / demultiplexer | | 模板:Unknown | (16) | SN74CBT3253 |- | 74x3257 | 4 | 4个 2-line to 1-line FET multiplexer / demultiplexer | | 模板:Unknown | (16) | IDT74FST3257 |- | 74x3283 | 1 | 32-bit latchable transceiver with parity checker / generator | | 三态逻辑 | (120) | 74ACTQ3283 |- | 74x3284 | 1 | 18-bit synchronous datapath multiplexer | | 三态逻辑 | (100) | 74ABT3284 |- | 74x3305 | 2 | 2个 FET bus switch with extended voltage range | | 模板:Unknown | (8) | SN74CBT3305C |- | 74x3306 | 2 | 2个 FET bus switch | | 模板:Unknown | (8) | SN74CBT3306 |- | 74x3345 | 1 | 8个 FET bus switch, 2个 output enable | | 模板:Unknown | (20) | SN74CBT3345 |- | 74x3374 | 1 | 8-bit metastable-resistant D-type flip-flop | | 三态逻辑 | 20 | SN74AS3374 |- | 74x3383 | 1 | 5-bit 4-port FET bus exchange switch | | 模板:Unknown | 24 | IDT74FST3383 |- | 74x3384 | 2 | 2个 5-bit FET bus switch | | 模板:Unknown | 24 | IDT74FST3384 |- | 74x3386 | 1 | 5-bit 4-port FET bus exchange switch with extended voltage range | | 模板:Unknown | (24) | SN74CBT3386 |- | 74x3390 | 1 | 8个 2-line to 1-line FET multiplexer / bus switch | | 模板:Unknown | (28) | IDT74FST3390 |- | 74x3573 | 1 | 8个 transparent latch | | 三态逻辑 | 20 | IDT74FCT3573 |- | 74x3574 | 1 | 8个 D-type flip flop | | 三态逻辑 | 20 | IDT74FCT3574 |- | 74x3584 | 2 | 2个 5-bit FET bus switch | | 模板:Unknown | 24 | QS74QST3584 |- | 74x3611 | 1 | 2304-bit FIFO memory (64x36) | | 三态逻辑 | (120) | SN74ABT3611 |- | 74x3612 | 1 | 4608-bit bidirectional FIFO memory (2x64x36) | | 三态逻辑 | (120) | SN74ABT3612 |- | 74x3613 | 1 | 2304-bit FIFO memory (64x36) | | 三态逻辑 | (120) | SN74ABT3613 |- | 74x3614 | 1 | 4608-bit bidirectional FIFO memory (2x64x36) | | 三态逻辑 | (120) | SN74ABT3614 |- | 74x3622 | 1 | 18432-bit bidirectional FIFO memory (2x256x36) | | 三态逻辑 | (120) | SN74ACT3622 |- | 74x3631 | 1 | 18432-bit FIFO memory (512x36) | | 三态逻辑 | (120) | SN74ACT3631 |- | 74x3632 | 1 | 36864-bit bidirectional FIFO memory (2x512x36) | | 三态逻辑 | (120) | SN74ACT3632 |- | 74x3638 | 1 | 32768-bit bidirectional FIFO memory (2x512x32) | | 三态逻辑 | (120) | SN74ACT3638 |- | 74x3641 | 1 | 36864-bit FIFO memory (1024x36) | | 三态逻辑 | (120) | SN74ACT3641 |- | 74x3642 | 1 | 73728-bit bidirectional FIFO memory (2x1024x36) | | 三态逻辑 | (120) | SN74ACT3642 |- | 74x3651 | 1 | 73728-bit FIFO memory (2048x36) | | 三态逻辑 | (120) | SN74ACT3651 |- | 74x3708 | 1 | 8192-bit PROM (1024x8) | | open-collector | 24 | SN74S3708 |- | 74x3807 | 1 | 1-to-10 clock driver | | driver | 20 | IDT74FCT3807 |- | 74x3827 | 1 | 10-bit buffer | | 三态逻辑 | 24 | IDT74FCT3827 |- | 74x3861 | 1 | 10-bit FET bus switch | | 模板:Unknown | (24) | SN74CBT3861 |- | 74x3862 | 1 | 10-bit FET bus switch with 2个 output enable | | 模板:Unknown | (24) | IDT74CBTLV3862 |- | 74x3893 | 1 | 4个 Futurebus backplane transceiver | | 三态逻辑 and open-collector | (20) | MC74F3893A |- | 74x3907 | 1 | Pentium clock synthesizer | | 三态逻辑 | (28) | IDT74FCT3907 |- | 74x3932 | 1 | PLL-based clock driver | | 三态逻辑 | (48) | IDT74FCT3932 |- ! 模板:TOC tab ! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |- | 74x4002 | 2 | 2个 4输入 NOR 或非门 | | | 14 | CD74HC4002 |- | 74x4015 | 2 | 2个 4-bit shift registers | | | 16 | CD74HC4015 |- | 74x4016 | 4 | 4个 bilateral switch | | analog | 14 | CD74HC4016 |- | 74x4017 | 1 | 5-stage ÷10 Johnson counter | | | 16 | CD74HC4017 |- | 74x4020 | 1 | 14-stage binary counter | | | 16 | SN74HC4020 |- | 74x4022 | 1 | 4-stage ÷8 Johnson counter | | | 14 | SN74HC4022 |- | 74x4024 | 1 | 7-stage ripple carry binary counter | | | 14 | CD74HC4024 |- | 74x4028 | 1 | BCD to decimal decoder | | | 16 | TC74HC4028P |- | 74x4040 | 1 | 12-stage binary ripple counter | | | 16 | SN74HC4040 |- | 74x4046 | 1 | phase-locked loop and voltage-controlled oscillator | | | 16 | CD74HC4046A |- | 74x4049 | 6 | 6个 inverting buffer | | | 16 | CD74HC4049 |- | 74x4050 | 6 | 6个 buffer/converter (non-inverting) | | | 16 | CD74HC4050 |- | 74x4051 | 1 | high-speed 8-channel analog multiplexer/demultiplexer | | analog | 16 | CD74HC4051 |- | 74x4052 | 2 | 2个 4-channel analog multiplexer/demultiplexers | | analog | 16 | CD74HC4052 |- | 74x4053 | 3 | 3个 2-channel analog multiplexer/demultiplexers | | analog | 16 | CD74HC4053 |- | 74x4059 | 1 | programmable divide-by-N counter | | | 24 | CD74HC4059 |- | 74x4060 | 1 | 14-stage binary ripple counter with oscillator | | | 16 | SN74HC4060 |- | 74x4061 | 1 | 14-stage asynchronous binary counter with oscillator | | | 16 | SN74HC4061 |- | 74x4066 | 4 | 4个 single-pole single-throw analog switch | | | 14 | SN74HC4066 |- | 74x4067 | 1 | 16-channel analog multiplexer/demultiplexer | | analog | 24 | CD74HC4067 |- | 74x4072 | 2 | 2个 4输入 OR或门 | | | 14 | TC74HC4072 |- | 74x4075 | 3 | 3个 3输入 OR或门 | | | 14 | CD74HC4075 |- | 74x4078 | 1 | 1个 8输入 OR或门/NOR 或非门 | | | 14 | MM74HC4078 |- | 74x4094 | 1 | 8-bit three-state shift register/latch | | 三态逻辑 | 16 | CD74HC4094 |- | 74x4102 | 1 | 2-digit BCD presettable synchronous down counter | | | 16 | 74HC4202 |- | 74x4103 | 1 | 8-bit binary presettable synchronous down counter | | | 16 | 74HC4203 |- | 74x4245 | 1 | 8-bit 3V/5V translating transceiver | | 三态逻辑 | (24) | 74LVX4245 |- | 74x4301 | 1 | 8-bit latch, inverting | | 三态逻辑 | 20 | MN74HC4301 |- | 74x4302 | 1 | 8-bit latch, non-inverting | | 三态逻辑 | 20 | MN74HC4302 |- | 74x4303 | 1 | 8-bit D-type flip-flop, inverting outputs | | 三态逻辑 | 20 | MN74HC4303 |- | 74x4304 | 1 | 8-bit D-type flip-flop, non-inverting outputs | | 三态逻辑 | 20 | MN74HC4304 |- | 74x4305 | 2 | 2个 4-bit buffer, inverting | | 三态逻辑 | 20 | MN74HC4305 |- | 74x4306 | 2 | 2个 4-bit buffer, non-inverting | | 三态逻辑 | 20 | MN74HC4306 |- | 74x4316 | 4 | 4个 analog switch | | analog | 14 | MM74HC4316 |- | 74x4351 | 1 | 8-channel analog multiplexer/demultiplexer with latch | | analog | 20 | CD74HC4351 |- | 74x4352 | 2 | 2个 4-channel analog multiplexer/demultiplexer with latch | | analog | 20 | CD74HC4352 |- | 74x4353 | 3 | 3个 2-channel analog multiplexer/demultiplexer with latch | | analog | 20 | MC74HC4353 |- | 74x4374 | 1 | 8-bit 2个-rank synchronizer | | 三态逻辑 | 20 | SN74AS4374 |- | 74x4503 | 1 | controller for 64k/256k/1M dynamic RAM | | 三态逻辑 | 52 | SN74ACT4503 |- | 74x4510 | 1 | BCD decade up/down counter | | | 16 | CD74HC4510 |- | 74x4511 | 1 | BCD to 7-segment decoder | | | 16 | CD74HC4511 |- | 74x4514 | 1 | 4-to-16 line decoder/demultiplexer, input latches | | | 24 | CD74HC4514 |- | 74x4515 | 1 | 4-to-16 line decoder/demultiplexer with input latches; inverting | | | 24 | CD74HC4515 |- | 74x4516 | 1 | 4-bit binary up/down counter | | | 16 | CD74HC4516 |- | 74x4518 | 2 | 2个 4-bit synchronous decade counter | | | 16 | CD74HC4518 |- | 74x4520 | 2 | 2个 4-bit synchronous binary counter | | | 16 | CD74HC4520 |- | 74x4538 | 2 | 2个 retriggerable precision monostable multivibrator | | | 16 | CD74HC4538 |- | 74x4543 | 1 | BCD to 7-segment latch/decoder/driver for LCDs | | | 16 | CD74HC4543 |- | 74x4560 | 1 | 4-bit BCD adder | | | 16 | MM74HC4560 |- | 74x4724 | 1 | 8-bit addressable latch | | | 16 | SN74HC4724 |- | 74x4764 | 1 | programmable dRAM controller | | | (100) | 74ABT4764 |- | 74x4799 | 1 | Timer for NiCd and NiMH chargers | Schmitt trigger | open-collector and three-state | 16 | 74LV4799 |- | 74x4851 | 1 | 8-channel analog multiplexer/demultiplexer | | analog | 16 | SN74HC4851 |- | 74x4852 | 2 | 2个 4-channel analog multiplexer/demultiplexer | | analog | 16 | SN74HC4852 |- | 74x5074 | 2 | 2个 positive edge-triggered D-type flip-flop (metastable immune) | | | 14 | 74ABT5074 |- | 74x5245 | 1 | 8个 bidirectional transceiver | Schmitt trigger | 三态逻辑 | 20 | DM74ALS5245 |- | 74x5300 | 1 | fiber optic LED driver | | driver 120 mA | 8 | 74F5300 |- | 74x5302 | 2 | 2个 fiber optic LED / clock driver | | driver 160 mA | 14 | 74F5302 |- | 74x5400 | 1 | 11-bit line/memory driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 28 | SN74ABT5400 |- | 74x5401 | 1 | 11-bit line/memory driver, inverting | | 三态逻辑, 25 Ω series resistor | 28 | SN74ABT5401 |- | 74x5402 | 1 | 12-bit line/memory driver, non-inverting | | 三态逻辑, 25 Ω series resistor | 28 | SN74ABT5402 |- | 74x5403 | 1 | 12-bit line/memory driver, inverting | | 三态逻辑, 25 Ω series resistor | 28 | SN74ABT5403 |- | 74x5555 | 1 | programmable delay timer with oscillator | | | 16 | 74HC5555 |- | 74x5620 | 1 | 8个 bidirectional transceiver | Schmitt trigger | 三态逻辑 | 20 | DM74ALS5620 |- ! 模板:TOC tab ! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |- | 74x6000 | 1 | logic-to-logic optocoupler, non-inverting | | | 6 | 74OL6000 |- | 74x6001 | 1 | logic-to-logic optocoupler, inverting | | | 6 | 74OL6001 |- | 74x6010 | 1 | logic-to-logic optocoupler, non-inverting | | open-collector 15 V | 6 | 74OL6010 |- | 74x6011 | 1 | logic-to-logic optocoupler, inverting | | open-collector 15 V | 6 | 74OL6011 |- | 74x6300 | 1 | programmable dynamic memory refresh timer | | | 16 | SN74ALS6300 |- | 74x6301 | 1 | dynamic memory refresh controller, transparent and burst modes, for 16K, 64K, 256K, and 1M dRAM | | | 52 | SN74ALS6301 |- | 74x6302 | 1 | dynamic memory refresh controller, transparent and burst modes, for 16K, 64K, 256K, and 1M dRAM | | | 52 | SN74ALS6302 |- | 74x6310 | 1 | static column and page mode access detector for dRAM | | | 20 | SN74ALS6310A |- | 74x6311 | 1 | static column and page mode access detector for dRAM | | | 20 | SN74ALS6311A |- | 74x6323 | 1 | programmable ripple counter with oscillator | | 三态逻辑 | (8) | 74HC6323A |- | 74x6364 | 1 | 64-bit flow-through error detection and correction circuit | | 三态逻辑 | (207) | SN74AS6364 |- | 74x6800 | 1 | 10-bit FET bus switch with precharge | | 模板:Unknown | 24 | IDT74FST6800 |- | 74x6845 | 1 | 8-bit FET bus switch with precharge and extended voltage range | | 模板:Unknown | (20) | SN74CBT6845C |- | 74x7001 | 4 | 4个 2输入 AND与门 | Schmitt trigger | | 14 | SN74HC7001 |- | 74x7002 | 4 | 4个 2输入 NOR 或非门 | Schmitt trigger | | 14 | SN74HC7002 |- | 74x7003 | 4 | 4个 2输入 NAND与非门 | Schmitt trigger | open-collector | 14 | SN74HC7003 |- | 74x7006 | 6 | two inverters, one 3输入 NAND, one 4输入 NAND, one 3输入 NOR, one 4输入 NOR | | | 24 | SN74HC7006 |- | 74x7007 | 6 | 6个 buffer gate | | | 14 | TC74HCT7007AP |- | 74x7008 | 6 | two inverters, three 2输入 NAND, three 2输入 NOR | | | 24 | SN74HC7008 |- | 74x7014 | 6 | 6个 buffer gate | Schmitt trigger | | 14 | 74HC7014 |- | 74x7022 | 1 | 4-stage ÷8 Johnson counter with power-up clear | | | 14 | SN74HC7022 |- | 74x7030 | 1 | 576-bit FIFO memory (64x9) | | 三态逻辑 | 28 | 74HC7030 |- | 74x7032 | 4 | 4个 2输入 OR或门s | Schmitt trigger | | 14 | SN74HC7032 |- | 74x7038 | 1 | 9-bit bus transceiver with latch | | 三态逻辑 | 24 | CD74HC7038 |- | 74x7046 | 1 | phase-locked loop with voltage-controlled oscillator and lock detector | | | 16 | CD74HC7046A |- | 74x7060 | 1 | 14-stage binary counter with oscillator | Schmitt trigger | | 20 | CD74AC7060 |- | 74x7074 | 6 | two inverters, one 2输入 NAND, one 2输入 NOR, two D-type flip-flops | | | 24 | SN74HC7074 |- | 74x7075 | 6 | two inverters, two 2输入 NAND, two D-type flip-flops | | | 24 | SN74HC7075 |- | 74x7076 | 6 | two inverters, two 2输入 NOR, two D-type flip-flops | | | 24 | SN74HC7076 |- | 74x7080 | 1 | 16-bit parity generator / checker | | | 20 | 74HCT7080 |- | 74x7132 | 4 | 4个 adjustable comparator with output latches | Schmitt trigger | 三态逻辑 | 14 | 74HCT7132 |- | 74x7200 | 1 | 2304-bit FIFO memory (256x9) | | | 28 | SN74ACT7200L |- | 74x7201 | 1 | 4608-bit FIFO memory (512x9) | | | 28 | SN74ACT7201LA |- | 74x7202 | 1 | 9216-bit FIFO memory (1024x9) | | | 28 | SN74ACT7202LA |- | 74x7203 | 1 | 18432-bit FIFO memory (2048x9) | | | 28 | SN74ACT7203L |- | 74ACT7204 | 1 | 36864-bit FIFO memory (4096x9) | | | 28 | SN74ACT7204L |- | 74HCU7204 | 2 | 2个 unbuffered inverters | | | (8) | SN74HCU7204 |- | 74x7205 | 1 | 73728-bit FIFO memory (8192x9) | | | 28 | SN74ACT7205L |- | 74x7206 | 1 | 147456-bit FIFO memory (16384x9) | | | 28 | SN74ACT7206L |- | 74x7240 | 1 | 8个 bus buffer, inverting | Schmitt trigger | 三态逻辑 | 20 | TC74HC7240AP |- | 74x7241 | 1 | 8个 bus buffer, non-inverting | Schmitt trigger | 三态逻辑 | 20 | TC74HC7241AP |- | 74x7244 | 1 | 8个 bus buffer, non-inverting | Schmitt trigger | 三态逻辑 | 20 | TC74HC7244AP |- | 74x7245 | 1 | 8个 bus transceiver, non-inverting | Schmitt trigger | 三态逻辑 | 20 | M74HC7245 |- | 74x7266 | 4 | 4个 2输入 XNOR异或非门 | | | 14 | SN74HC7266 |- | 74x7273 | 8 | 8个 positive edge-triggered D-type flip-flop with reset | | open-collector | 20 | 74HCT7273 |- | 74x7292 | 1 | programmable divider/timer | | | 16 | TC74HC7292AP |- | 74x7294 | 1 | programmable divider/timer | | | 16 | M74HC7294 |- | 74x7340 | 1 | 8-bit bus driver with bidirectional registers | | 三态逻辑 | 24 | SN74HC7340 |- | 74x7403 | 1 | 256-bit FIFO memory (64x4) | | 三态逻辑 | 16 | 74HC7403 |- | 74x7404 | 1 | 320-bit FIFO memory (64x5) | | 三态逻辑 | 18 | 74HC7404 |- | 74x7540 | 8 | 8个 buffer/line driver, inverting | Schmitt trigger | 三态逻辑 | 20 | 74HC7540 |- | 74x7541 | 8 | 8个 buffer/line driver, non-inverting | Schmitt trigger | 三态逻辑 | 20 | 74HC7541 |- | 74x7597 | 1 | 8-bit shift register with input latches | | | 16 | 74HC7597 |- | 74x7623 | 1 | 8个 bus transceiver, non-inverting | | 三态逻辑 and open-drain | 20 | CD74AC7623 |- | 74x7640 | 1 | 8个 bus transceiver, inverting | Schmitt trigger | 三态逻辑 | 20 | M74HC7640 |- | 74x7643 | 1 | 8个 bus transceiver, non-inverting/inverting | Schmitt trigger | 三态逻辑 | 20 | M74HC7643 |- | 74x7645 | 1 | 8个 bus transceiver, non-inverting | Schmitt trigger | 三态逻辑 | 20 | M74HC7645 |- | 74x7731 | 4 | 4个 64-bit static shift register | | | 16 | 74HC7731 |- | 74x7793 | 1 | 8-bit noninverting transparent latch with readback | | 三态逻辑 | 20 | MC74HC7793 |- | 74x7801 | 1 | 18432-bit FIFO memory (1024x18), clocked | | 三态逻辑 | (68) | SN74ACT7801 |- | 74x7802 | 1 | 18432-bit FIFO memory (1024x18) | | 三态逻辑 | (68) | SN74ACT7802 |- | 74x7803 | 1 | 9216-bit FIFO memory (512x18), clocked | | 三态逻辑 | (56) | SN74ACT7803 |- | 74x7804 | 1 | 9216-bit FIFO memory (512x18) | | 三态逻辑 | (56) | SN74ACT7804 |- | 74x7805 | 1 | 4608-bit FIFO memory (256x18), clocked | | 三态逻辑 | (56) | SN74ACT7805 |- | 74x7806 | 1 | 4608-bit FIFO memory (256x18) | | 三态逻辑 | (56) | SN74ACT7806 |- | 74x7807 | 1 | 18432-bit FIFO memory (2048x9), clocked | | 三态逻辑 | (44) | SN74ACT7807 |- | 74x7808 | 1 | 18432-bit FIFO memory (2048x9) | | 三态逻辑 | (44) | SN74ACT7808 |- | 74x7811 | 1 | 18432-bit FIFO memory (1024x18), clocked | | 三态逻辑 | (68) | SN74ACT7811 |- | 74x7813 | 1 | 1152-bit FIFO memory (64x18), clocked | | 三态逻辑 | (56) | SN74ACT7813 |- | 74x7814 | 1 | 1152-bit FIFO memory (64x18) | | 三态逻辑 | (56) | SN74ACT7814 |- | 74x7815 | 1 | 4608-bit bidirectional FIFO memory(2x64x36) | | 三态逻辑 | (120) | SN74ABT7815 |- | 74x7816 | 1 | 4608-bit bidirectional FIFO memory(2x64x36) | | 三态逻辑 | (120) | SN74ABT7816 |- | 74x7817 | 1 | 2304-bit FIFO memory(64x36) | | 三态逻辑 | (120) | SN74ABT7817 |- | 74x7818 | 1 | 2304-bit FIFO memory(64x36) | | 三态逻辑 | (120) | SN74ABT7818 |- | 74x7819 | 1 | 18432-bit bidirectional FIFO memory (2x512x18), clocked | | 三态逻辑 | (80) | SN74ABT7819 |- | 74x7820 | 1 | 18432-bit bidirectional FIFO memory (2x512x18) | | 三态逻辑 | (80) | SN74ABT7820 |- | 74x7821 | 1 | 32768-bit bidirectional FIFO memory (2x512x32) | | 三态逻辑 | (120) | SN74ACT7821 |- | 74x7822 | 1 | 32768-bit bidirectional FIFO memory (2x512x32), clocked | | 三态逻辑 | (120) | SN74ACT7822 |- | 74x7823 | 1 | 36864-bit FIFO memory (1024x36), clocked | | 三态逻辑 | (120) | SN74ACT7823 |- | 74x7881 | 1 | 18432-bit FIFO memory (1024x18), clocked | | 三态逻辑 | (68) | SN74ACT7881 |- | 74x7882 | 1 | 36864-bit FIFO memory (2048x18), clocked | | 三态逻辑 | (68) | SN74ACT7882 |- | 74x7884 | 1 | 73728-bit FIFO memory (4096x18), clocked | | 三态逻辑 | (68) | SN74ACT7884 |- | 74x8003 | 2 | 2个 2输入 NAND与非门 | | | 8 | SN74ALS8003 |- | 74x8151 | 1 | 10-bit inverting/non-inverting buffer | Schmitt trigger | 三态逻辑 | 24 | SN74LV8151 |- | 74x8153 | 1 | 8-bit serial-to-parallel interface | | 三态逻辑 or open-collector | 20 | SN74LV8153 |- | 74x8154 | 2 | 2个 16-bit counters with output registers | | 三态逻辑 | 20 | SN74LV8154 |- | 74x8161 | 1 | 8-bit synchronous binary counter | | | 24 | SN74ALS8161 |- | 74x8240 | 1 | 8个 inverting buffer with JTAG port | | 三态逻辑 | 24 | SN74BCT8240A |- | 74x8244 | 1 | 8个 non-inverting buffer with JTAG port | | 三态逻辑 | 24 | SN74BCT8244A |- | 74x8245 | 1 | 8个 bus transceiver with JTAG port | | 三态逻辑 | 24 | SN74ABT8245 |- | 74x8373 | 1 | 8个 D-type latch with JTAG port | | 三态逻辑 | 24 | SN74BCT8373A |- | 74x8374 | 1 | 8个 D-type edge-triggered flip-flop with JTAG port | | 三态逻辑 | 24 | SN74BCT8374A |- | 74x8400 | 1 | expandable error checker / corrector | | 三态逻辑 | 48 | SN74ALS8400 |- | 74x8541 | 1 | 8-bit buffer, selectable inverting/non-inverting | Schmitt trigger | 三态逻辑 | 20 | SN74AHC8541 |- | 74x8543 | 1 | 8个 registered bus transceiver with JTAG port | | 三态逻辑 | 28 | SN74ABT8543 |- | 74x8646 | 1 | 8个 bus transceiver and register with JTAG port | | 三态逻辑 | 28 | SN74ABT8646 |- | 74x8652 | 1 | 8个 bus transceiver and register with JTAG port | | 三态逻辑 | 28 | SN74ABT8652 |- | 74x8818 | 1 | 16-bit microprogram sequencer, cascadable | | 三态逻辑 | (84) | SN74ACT8818 |- | 74x8832 | 1 | 32-bit registered ALU | | 三态逻辑 | (208) | SN74ACT8832 |- | 74x8834 | 1 | 40-bit register file | | 三态逻辑 | (156) | SN74AS8834 |- | 74x8835 | 1 | 16-bit microprogram sequencer, cascadable | | 三态逻辑 | (156) | SN74AS8835 |- | 74x8836 | 1 | 32x32-bit multiplier/accumulator | | 三态逻辑 | (156) | SN74ACT8836 |- | 74x8837 | 1 | 64-bit floating point unit | | 三态逻辑 | (208) | SN74ACT8837 |- | 74x8838 | 1 | 64-bit barrel shifter | | 三态逻辑 | (84) | SN74AS8838 |- | 74x8839 | 1 | 32-bit shuffle/exchange network | | 三态逻辑 | (85) | SN74AS8839 |- | 74x8840 | 1 | digital crossbar switch | | 三态逻辑 | (156) | SN74AS8840 |- | 74x8841 | 1 | digital crossbar switch | | 三态逻辑 | (156) | SN74ACT8841 |- | 74x8847 | 1 | 64-bit floating point and integer unit | | 三态逻辑 | (208) | SN74ACT8847 |- | 74x8867 | 1 | 32-bit vector processor unit | | 三态逻辑 | (208) | SN74ACT8867 |- | 74x8952 | 1 | 8个 registered bus transceiver with JTAG port | | 三态逻辑 | 28 | SN74ABT8952 |- | 74x8960 | 1 | 8-bit bidirectional latched FutureBus transceiver, inverting | | 三态逻辑 and open-collector | 28 | 74F8960 |- | 74x8961 | 1 | 8-bit bidirectional latched FutureBus transceiver, non-inverting | | 三态逻辑 and open-collector | 28 | 74F8961 |- | 74x8962 | 1 | 9-bit bidirectional latched FutureBus transceiver, inverting | | 三态逻辑 and open-collector | (44) | 74F8962 |- | 74x8963 | 1 | 9-bit bidirectional latched FutureBus transceiver, non-inverting | | 三态逻辑 and open-collector | (44) | 74F8963 |- | 74x8965 | 1 | 9-bit bidirectional latched FutureBus transceiver, latch select | | 三态逻辑 and open-collector | (44) | 74F8965 |- | 74x8966 | 1 | 9-bit bidirectional latched FutureBus transceiver, idle arbitration request / output | | 三态逻辑 and open-collector | (44) | 74F8966 |- | 74x8980 | 1 | JTAG test access port master with 8-bit host interface | | 三态逻辑 | 24 | SN74LVT8980 |- | 74x8986 | 1 | linkable, multidrop-addressable JTAG transceiver | | 三态逻辑 | (64) | SN74LVT8986 |- | 74x8990 | 1 | JTAG test access port master with 16-bit host interface | | 三态逻辑 | (44) | SN74ACT8990 |- | 74x8994 | 1 | JTAG scan-controlled logic/signature analyzer | | | (28) | SN74ACT8994 |- | 74x8996 | 1 | multidrop-addressable JTAG transceiver | | | 24 | SN74ABT8996 |- | 74x8997 | 1 | scan-controlled JTAG concatenator | | 三态逻辑 | 28 | SN74ACT8997 |- | 74x8999 | 1 | scan-controlled JTAG multiplexer | | 三态逻辑 | 28 | SN74ACT8999 |- | 74x9000 | 1 | programmable timer with oscillator | | | 20 | MC74HC9000 |- | 74x9014 | 9 | nine-wide buffer/line driver, inverting | Schmitt trigger | | 20 | 74HC9014 |- | 74x9015 | 9 | nine-wide buffer/line driver, non-inverting | Schmitt trigger | | 20 | 74HC9015 |- | 74x9034 | 9 | nine-wide buffer, inverting | | | 20 | MC74HC9034 |- | 74x9035 | 9 | nine-wide buffer, noninverting | | | 20 | MC74HC9035 |- | 74x9046 | 1 | PLL with band gap controlled VCO | | | 16 | 74HCT9046 |- | 74x9114 | 9 | nine-wide inverter | Schmitt trigger | open-collector | 20 | 74HC9114 |- | 74x9115 | 9 | nine-wide buffer | Schmitt trigger | open-collector | 20 | 74HC9115 |- | 74x9134 | 9 | nine-wide buffer, inverting | | open-collector | 20 | MC74HC9134 |- | 74x9135 | 9 | nine-wide buffer, noninverting | | open-collector | 20 | MC74HC9135 |- | 74x9164 | 1 | 8-bit shift register (serial in/out, parallel in/out) | Schmitt trigger | 三态逻辑 | (16) | TC74VHC9164 |- | 74x9240 | 1 | 9-bit buffer / line driver, inverting | | 三态逻辑 | 24 | 74FR9240 |- | 74x9244 | 1 | 9-bit buffer / line driver, non-inverting | | 三态逻辑 | 24 | 74FR9244 |- | 74x9245 | 1 | 9-bit bidirectional transceiver, non-inverting | | 三态逻辑 | 24 | 74FR9245 |- | 74x9323 | 1 | programmable ripple counter with oscillator | | 三态逻辑 | (8) | 74HC9323A |- | 74x9510 | 1 | 16×16-bit multiplier/accumulator (compatible to Am29510 and TDC1010) | | 三态逻辑 | (68) | 74HC9510<ref name=hcmostb/>模板:Rp |- | 74x9595 | 1 | 8-bit shift register with latch (serial in, parallel out) | Schmitt trigger | | (16) | TC74VHC9595 |- | 74x40102 | 1 | presettable synchronous 2-decade BCD down counter | | | 16 | CD74HC40102 |- | 74x40103 | 1 | presettable 8-bit synchronous down counter | | | 16 | CD74HC40103 |- | 74x40104 | 4 | 4-bit bidirectional universal shift register | | 三态逻辑 | 16 | CD74HC40104 |- | 74x40105 | 1 | 64-bit FIFO memory (16x4) | | 三态逻辑 | 16 | CD74HC40105 |- ! 芯片型号 !! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册 |}

Smaller footprints

As board designs have migrated away from large amounts of logic chips, so has the need for many of the same gate in one package. Since about 1996,<ref>{{

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All chips in the following sections are available 5- to 10-pin surface-mount packages. The right digits, after the 1G/2G/3G, typically has the same functional features as older legacy chips, except for the multifunctional chips and 4-digit chip numbers, which are unique to these newer families. The "x" in the part number is a place holder for the logic family name. For example, 74x1G14 in "LVC" logic family would be "74LVC1G14". The previously stated prefixes of "SN-" and "MC-" are used to denote manufacturers, Texas Instruments and ON Semiconductor respectively.<ref name="TI-L-LG">2018 Little Logic Guide; Texas Instruments.</ref><ref name="NXP-AUP-LG">74AUP Logic Guide; NXP.</ref><ref name="NXP-LVC-LG">74LVC Logic Guide; NXP.</ref>

Some of the manufacturers that make these smaller IC chips are: Diodes Incorporated, Nexperia (NXP Semiconductors), ON Semiconductor (Fairchild Semiconductor), Texas Instruments (National Semiconductor), Toshiba.

The logic families available in small footprints are: AHC, AHCT, AUC, AUP, AXP, HC, HCT, LVC, VHC, NC7S, NC7ST, NC7SU, NC7SV. The LVC family is very popular in small footprints because it supports the most common logic voltages of 1.8 V, 3.3 V, 5 V, its inputs are 5 V tolerant when the device is powered at a lower voltage, and an output drive of 24 mA. Gates that are commonly available across most small footprint families are 00, 02, 04, 08, 14, 32, 86, 125, 126.

One-gate chips

All chips in this section have one gate, noted by the "1G" in the part numbers.

芯片型号	描述	输入	输出	Pin数目	数据手册
74x1G00	1个 2输入与非门			5	LVC
74x1G02	1个 2输入 NOR 或非门			5	LVC
74x1G04	1个非门			5	LVC
74x1G06	1个非门	schmitt trigger	open-drain	5	LVC
74x1G07	1个 buffer gate	schmitt trigger	open-drain	5	LVC
74x1G08	1个 2输入 AND gate			5	LVC
74x1G09	1个 2输入 AND与门		open-drain	5	AUP
74x1G10	1个 3输入 NAND与非门			6	LVC
74x1G11	1个 3输入 AND与门			6	LVC
74x1G14	1个非门	schmitt trigger		5	LVC
74x1G17	1个 buffer gate	schmitt trigger		5	LVC
74x1G18	1个 1-of-2 non-inverting multiplexer, deselected output is 3-state		三态逻辑	6	LVC
74x1G19	1个 1-to-2 line decoder, active low outputs			6	LVC
74x1G27	1个 3输入 NOR 或非门			6	LVC
74x1G29	1个 2-to-3 line decoder, active low outputs			8	LVC
74x1G32	1个 2输入 OR gate			5	LVC
74x1G34	1个 buffer gate			5	LVC
74x1G38	1个 2输入 NAND与非门		open-drain	5	LVC
74x1G57	1个 configurable 7-function gate	schmitt trigger		6	LVC
74x1G58	1个 configurable 7-function gate	schmitt trigger		6	LVC
74x1G66	1个 SPST analog switch	analog	analog	5	LVC
74x1G74	1个 D-type flip-flop, positive-edge trigger, Q & 模板:Overline outputs, asynchronous preset and clear			8	LVC
74x1G79	1个 D-type flip-flop, positive-edge trigger, Q output			5	LVC
74x1G80	1个 D-type flip-flop, positive-edge trigger, 模板:Overline output			5	LVC
74x1G86	1个 2输入 XOR gate (a.k.a. 2-bit even-parity generator)			5	LVC
74x1G97	1个 configurable 7-function gate	schmitt trigger		6	LVC
74x1G98	1个 configurable 7-function gate	schmitt trigger		6	LVC
74x1G99	1个 configurable 15-function gate, active-low enable	schmitt trigger	三态逻辑	8	LVC
74x1G123	1个 retriggerable monostable multivibrator, active-low clear			8	LVC
74x1G125	1个 buffer gate, active-low enable		三态逻辑	5	LVC
74x1G126	1个 buffer gate, active-high enable		三态逻辑	5	LVC
74x1G132	1个 2输入 NAND与非门	schmitt trigger		5	LVC
74x1G139	1个 2-to-4 line decoder, active low outputs			8	LVC
74x1G157	1个 2输入 multiplexer	schmitt trigger		6	LVC
74x1G158	1个 2输入 multiplexer, inverted output	schmitt trigger		6	AUP
74x1G175	1个 D-type flip-flop, positive-edge trigger, Q output, asynchronous clear			6	LVC
74x1G240	1个非门, active-low enable		三态逻辑	5	LVC
74x1G332	1个 3输入 OR或门			6	LVC
74x1G373	1个 D-type transparent latch, negative-edge latching, Q output, active-low enable		三态逻辑	6	LVC
74x1G374	1个 D-type flip-flop, positive-edge trigger, Q output, active-low enable		三态逻辑	6	LVC
74x1G386	1个 3输入 XOR异或门 (a.k.a. 3-bit even-parity generator)			6	LVC
74x1G0832	1个 3输入 AND-OR combo gate (2输入 AND into 2输入 OR)	schmitt trigger		6	LVC
74x1G3157	1个 SPDT analog switch	analog	analog	6	LVC
74x1G3208	1个 3输入 OR-AND combo gate (2输入 OR into 2输入 AND)	schmitt trigger		6	LVC

Two-gate chips

All chips in this section have two gates, noted by the "2G" in the part numbers.

芯片型号	描述	输入	输出	Pin数目	数据手册
74x2G00	2个 2输入 NAND与非门			8	LVC
74x2G02	2个 2输入 NOR 或非门			8	LVC
74x2G04	2个非门			6	LVC
74x2G06	2个非门	schmitt trigger	open-drain	6	LVC
74x2G07	2个 buffer gate	schmitt trigger	open-drain	6	LVC
74x2G08	2个 2输入 AND与门			8	LVC
74x2G14	2个非门	schmitt trigger		6	LVC
74x2G17	2个 buffer gate	schmitt trigger		6	LVC
74x2G32	2个 2输入 OR或门			8	LVC
74x2G34	2个 buffer gate			6	LVC
74x2G38	2个 2输入 NAND与非门		open-drain	8	LVC
74x2G57	2个 configurable 7-function gate	schmitt trigger		10	AUP
74x2G58	2个 configurable 7-function gate	schmitt trigger		10	AUP
74x2G66	2个 SPST analog switch	analog	analog	8	LVC
74x2G79	2个 D-type flip-flop, positive-edge trigger, Q output			8	LVC
74x2G80	2个 D-type flip-flop, positive-edge trigger, 模板:Overline output			8	LVC
74x2G86	2个 2输入 XOR异或门 (a.k.a. 2-bit even-parity generator)			8	LVC
74x2G97	2个 configurable 7-function gate	schmitt trigger		10	AUP
74x2G98	2个 configurable 7-function gate	schmitt trigger		10	AUP
74x2G125	2个 buffer, active-low enable		三态逻辑	8	LVC
74x2G126	2个 buffer, active-high enable		三态逻辑	8	LVC
74x2G132	2个 2输入 NAND与非门	schmitt trigger		8	LVC
74x2G240	2个非门, active-low enable		三态逻辑	8	LVC
74x2G241	2个 buffer, active-low and active-high enables		三态逻辑	8	LVC
74x2G0604	2个 combo gates - one inverter, one inverter with O.D.		open-drain	6	AUP
74x2G3404	2个 combo gates - one buffer, one inverter			6	AUP
74x2G3407	2个 combo gates - one buffer, one buffer with O.D.		open-drain	6	AUP

Three-gate chips

All chips in this section have three gates, noted by the "3G" in the part numbers.

芯片型号	描述	输入	输出	Pin数目	数据手册
74x3G04	3个非门			8	LVC
74x3G06	3个非门	schmitt trigger	open-drain	8	LVC
74x3G07	3个 buffer gate	schmitt trigger	open-drain	8	LVC
74x3G14	3个非门	schmitt trigger		8	LVC
74x3G16	3个 buffer gate			8	LVC
74x3G17	3个 buffer gate	schmitt trigger		8	LVC
74x3G34	3个 buffer gate			8	LVC
74x3G0434	3个 combo gates - two inverter, one buffer			8	AUP
74x3G3404	3个 combo gates - two buffer, one inverter			8	AUP

Voltage translation

All chips in this section have two power-supply pins to translate unidirectional logic signals between two different logic voltages. The logic families that support 2个-supply voltage translation are AVC, AVCH, AXC, AXCH, AXP, LVC, where the "H" in AVCH and AXCH means "bus hold" feature.

芯片型号	描述	Pin数量	AXC	AXP	LVC
74x1T45	1 buffer	6	AXC	AXP	LVC
74x2T45	2 buffers	8	AXC	AXP	LVC
74x4T245	4 buffers	16	AXC	AXP	n/a
74x8T245	8 buffers	24	AXC	AXP	LVC
74x16T245	16 buffers	48	n/a	n/a	LVC

Chips in the above table support the following voltage ranges on either power supply pin:

AXC = 0.65 to 3.6 V. Only available from Texas Instruments.
AXP = 0.9 to 5.5 V. Only available from Nexperia.
LVC = 1.65 to 5.5 V. Available from Diodes Inc, Nexperia, Texas Instruments.

References

1 | references-column-count references-column-count-{{{1}}} }} }} }}" {{#if: | style="-moz-column-width:{{{colwidth}}}; column-width:{{{colwidth}}};" | {{#if: | style="-moz-column-count:{{{1}}}; column-count:{{{1}}};" }} }}> <references group=""></references>

沙盒：修订间差异

2022年6月11日 (六) 23:17的版本

目录

概述

逻辑门

较多pin脚的芯片

Smaller footprints

One-gate chips

Two-gate chips

Three-gate chips

Voltage translation

See also

References

Further reading

导航菜单

页面操作

页面操作

个人工具

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@@ 第12行： / 第12行： @@
 Conversely, the 4000-series has "borrowed" from the 7400 series{{snd}} such as the CD40193 and CD40161 being pin-for-pin ''functional'' replacements for 74C193 and 74C161.
-Older TTL parts made by manufacturers such as [[Signetics]], [[Motorola]], [[Mullard]] and [[Siemens]] may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8输入 [[NAND gate]] like a 7430.
+Older TTL parts made by manufacturers such as [[Signetics]], [[Motorola]], [[Mullard]] and [[Siemens]] may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8输入 [[与非门]] like a 7430.
 A few alphabetic characters to designate a specific [[7400-series integrated circuits#Families|logic subfamily]] may immediately follow the '''74''' or '''54''' in the part number, e.g., 74LS74 for low-power [[Schottky diode|Schottky]]. Some CMOS parts such as 74HCT74 for high-speed [[CMOS]] with TTL-compatible input thresholds are functionally similar to the TTL part. Not all functions are available in all families.
@@ 第104行： / 第104行： @@
 * SN54LS54 = single 2-3-3-2 AOI gate
-==Larger footprints==
+==较多pin脚的芯片==
-Parts in this section have a pin count of 14 pins or more.  The lower part numbers were established in the 1960s and 1970s, then higher part numbers were added incrementally over decades.  IC manufacturers continue to make a core subset of this group, but many of these part numbers are considered obsolete and no longer manufactured.  Older discontinued parts may be available from a limited number of sellers as [[new old stock]] (NOS), though some are much harder to find.
+本节中的器件的引脚数为14个及以上。较小芯片编号是在20世纪60年代和70年代发布的，然后几十年来逐步有更高的芯片编号。IC制造商继续制造那些广泛使用的芯片，而其他许多芯片编号被认为是过时的，并不再生产了。较旧的芯片型号可能从有限的卖家处获得，比如 [[new old stock]](NOS)即新的原始库存，尽管有些芯片型号更难找到。
+对于下表：
+* 芯片型号列{{snd}} "x"是 [[7400-series integrated circuits#Families|logic subfamily]] 的占位符. 例如，74x00芯片在“LS”逻辑系列中就是“74LS00”。
+* 描述列{{snd}} 包括术语施密特触发器、集电极开路/漏极开路、三态被移动到输入列和输出列，以便更容易地按这些特征进行排序。
+* 输入列{{snd}} 空白单元格表示正常输入。
+* 输出列{{snd}} 空白单元格表示"totem pole" 输出，也称为 [[push–pull output]]，能够驱动同一逻辑子类芯片的十个标准输入 ([[fan-out]] N<sub>O</sub>&nbsp;=&nbsp;10). 具有更高输出电流的芯片型号通常称为驱动器或缓冲器。
+* Pin数目列{{snd}} [[雙列直插封裝]] (DIP) 封装的pin脚数目; 括号（圆括号）中的数字表示该 IC 没有已知的双列直插式封装版本。
-For the following table:
-* Part number column{{snd}} the "x" is a place holder for the [[7400-series integrated circuits#Families|logic subfamily]] name. For example, 74x00 in "LS" logic family would be "74LS00".
-* Description column{{snd}} the terms Schmitt trigger, open-collector/open-drain, three-state were moved to the input and output columns to make it easier to sort by those features.
-* Input column{{snd}} a blank cell means a normal input for the logic family type.
-* Output column{{snd}} a blank cell means a "totem pole" output, also known as a [[push–pull output]], with the ability to drive ten standard inputs of the same logic subfamily ([[fan-out]] N<sub>O</sub>&nbsp;=&nbsp;10). Outputs with higher output currents are often called drivers or buffers.
-* Pins column{{snd}} number of pins for the [[2个 in-line package]] (DIP) version; a number in [[parentheses]] (round brackets) indicates that there is no known 2个 in-line package version of this IC.
 {|class="wikitable sortable"
@@ 第120行： / 第123行： @@
 | 74x00
 | 4
-| 4个 2输入 [[NAND gate]]
+| 4个 2输入 [[与非门|NAND与非门]]
 |
 |
@@ 第1,221行： / 第1,224行： @@
 | 4个 bus buffer, negative enable
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 14
 | [http://www.ti.com/lit/gpn/sn74ls126a SN74LS125A]
@@ 第1,229行： / 第1,232行： @@
 | 4个 bus buffer, positive enable
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 14
 | [http://www.ti.com/lit/gpn/sn74ls126a SN74LS126A]
@@ 第1,285行： / 第1,288行： @@
 | 1个 12输入 NAND与非门
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [http://www.ti.com/lit/gpn/sn54s134 SN74S134]
@@ 第1,589行： / 第1,592行： @@
 | 16-bit multiple port register file (8x2)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n729 SN74172]
@@ 第1,597行： / 第1,600行： @@
 | 4个 D flip-flop, asynchronous clear
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [http://www.ti.com/lit/gpn/sn54ls173a SN74173]
@@ 第1,725行： / 第1,728行： @@
 | 64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n191 SN74S189]
@@ 第1,816行： / 第1,819行： @@
 | 256-bit RAM (256x1)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n299 DM74S200]
@@ 第1,824行： / 第1,827行： @@
 | 256-bit RAM (256x1)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n195 SN74S201]
@@ 第1,832行： / 第1,835行： @@
 | 256-bit RAM (256x1) with power down
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBook2ed05_2617547/page/n51 SN74LS202]
@@ 第1,848行： / 第1,851行： @@
 | 1024-bit RAM (256x4)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS207]
@@ 第1,856行： / 第1,859行： @@
 | 1024-bit RAM (256x4), separate data in- and outputs
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS208]
@@ 第1,864行： / 第1,867行： @@
 | 1024-bit RAM (1024x1)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookmoryDataBook1975_9924035/page/nductor_Memory_Data_Book_1975#page/n171 SN74S209]
@@ 第1,872行： / 第1,875行： @@
 | 8个 buffer, inverting
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n311 SN74LS210]
@@ 第1,880行： / 第1,883行： @@
 | 144-bit RAM (16x9) with output latch
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n181 74F211]
@@ 第1,888行： / 第1,891行： @@
 | 144-bit RAM (16x9)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n185 74F212]
@@ 第1,896行： / 第1,899行： @@
 | 192-bit RAM (16x12)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n189 74F213]
@@ 第1,904行： / 第1,907行： @@
 | 1024-bit RAM (1024x1)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS214]
@@ 第1,912行： / 第1,915行： @@
 | 1024-bit RAM (1024x1) with power-down mode
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS215]
@@ 第1,920行： / 第1,923行： @@
 | 256-bit RAM (64x4), common I/O
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044696.pdf SN74LS216]
@@ 第1,928行： / 第1,931行： @@
 | 256-bit RAM (64x4)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS217]
@@ 第1,936行： / 第1,939行： @@
 | 256-bit RAM (32x8)
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS218]
@@ 第1,944行： / 第1,947行： @@
 | 64-bit RAM (16x4), non-inverting outputs
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/stream/SupplementToTheTTLDataBookForDesignEngineers2ndEdition/Supplement%20to%20The%20TTL%20Data%20Book%20for%20Design%20Engineers_2nd_Edition#page/n5 SN74LS219]
@@ 第1,960行： / 第1,963行： @@
 | 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous, input/output ready enable
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS222]
@@ 第1,968行： / 第1,971行： @@
 | 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS224]
@@ 第1,976行： / 第1,979行： @@
 | 80-bit FIFO memory (16x5), asynchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [http://www.ti.com/lit/gpn/sn74s225 SN74S225]
@@ 第1,984行： / 第1,987行： @@
 | 4-bit parallel latched bus transceiver
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n219 SN74S226]
@@ 第2,008行： / 第2,011行： @@
 | 80-bit FIFO memory (16x5), asynchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://web.archive.org/web/20070101063514/http://focus.ti.com/lit/ds/symlink/sn74als229b.pdf SN74ALS229B]
@@ 第2,016行： / 第2,019行： @@
 | 2个 4-bit buffer/driver, one inverted, one non-inverted; negative enable
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS230]
@@ 第2,024行： / 第2,027行： @@
 | 2个 4-bit buffer/driver, both inverted; one positive and one negative enable
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS231]
@@ 第2,032行： / 第2,035行： @@
 | 64-bit FIFO memory (16x4), asynchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [http://www.ti.com/lit/gpn/sn74als232b SN74ALS232B]
@@ 第2,040行： / 第2,043行： @@
 | 80-bit FIFO memory (16x5), asynchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n101 SN74ALS233B]
@@ 第2,048行： / 第2,051行： @@
 | 256-bit FIFO memory (64x4), asynchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n63 SN74ALS234]
@@ 第2,056行： / 第2,059行： @@
 | 320-bit FIFO memory (64x5), asynchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 20
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n109 SN74ALS235]
@@ 第2,064行： / 第2,067行： @@
 | 256-bit FIFO memory (64x4), asynchronous
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 16
 | [https://web.archive.org/web/20070102044700/http://focus.ti.com/lit/ds/symlink/sn74als236.pdf SN74ALS236]
@@ 第2,096行： / 第2,099行： @@
 | 8个 buffer, inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls240 SN74LS240]
@@ 第2,104行： / 第2,107行： @@
 | 8个 buffer, non-inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls240 SN74LS241]
@@ 第2,112行： / 第2,115行： @@
 | 4个 bus transceiver, inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 14
 | [https://web.archive.org/web/20040608202058/http://focus.ti.com/lit/ds/symlink/sn74ls242.pdf SN74LS242]
@@ 第2,120行： / 第2,123行： @@
 | 4个 bus transceiver, non-inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 14
 | [http://www.ti.com/lit/gpn/sn74ls243 SN74LS243]
@@ 第2,128行： / 第2,131行： @@
 | 8个 buffer, non-inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls240 SN74LS244]
@@ 第2,136行： / 第2,139行： @@
 | 8个 bus transceiver, non-inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls245 SN74LS245]
@@ 第2,176行： / 第2,179行： @@
 | 1 of 16 data selector/multiplexer
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n273 SN74AS250]
@@ 第2,184行： / 第2,187行： @@
 | 8-line to 1-line data selector/multiplexer, complementary outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn74ls251 SN74251]
@@ 第2,192行： / 第2,195行： @@
 | 2个 4-line to 1-line data selector/multiplexer
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn74ls253 SN74LS253]
@@ 第2,200行： / 第2,203行： @@
 | 2个 2-to-4 line decoder/demultiplexer, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_icMaster19_198675341/page/n315 74LS255]
@@ 第2,216行： / 第2,219行： @@
 | 4个 2-line to 1-line data selector/multiplexer, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn74ls257b SN74LS257B]
@@ 第2,224行： / 第2,227行： @@
 | 4个 2-line to 1-line data selector/multiplexer, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn74ls257b SN74LS258B]
@@ 第2,256行： / 第2,259行： @@
 | 5760-bit ROM ([[Teletext]] character set, 128 characters 5x9)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044628.pdf SN74S262N]
@@ 第2,288行： / 第2,291行： @@
 | 6个 D-type latches, common output control, common enable
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n935 SN74S268]
@@ 第2,328行： / 第2,331行： @@
 | 4-bit by 4-bit binary multiplier
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S274]
@@ 第2,336行： / 第2,339行： @@
 | 7-bit slice [[Wallace tree]]
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S275]
@@ 第2,424行： / 第2,427行： @@
 | 1024-bit [[programmable read-only memory|PROM]] (256x4)
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S287]
@@ 第2,432行： / 第2,435行： @@
 | 256-bit [[programmable read-only memory|PROM]] (32x8)
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S288]
@@ 第2,480行： / 第2,483行： @@
 | 4-bit bidirectional shift register
 |
-| three-state
+| 三态逻辑
 | 14
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n989 SN74LS295B]
@@ 第2,504行： / 第2,507行： @@
 | 8-bit bidirectional universal shift/storage register
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls299 SN74LS299]
@@ 第2,571行： / 第2,574行： @@
 | 8个 buffer, inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n315 SN74LS310]
@@ 第2,667行： / 第2,670行： @@
 | 8-bit shift register, sign extend
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1013 SN74LS322A]
@@ 第2,675行： / 第2,678行： @@
 | 8-bit bidirectional universal shift/storage register, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls323 SN74LS323]
@@ 第2,715行： / 第2,718行： @@
 | [[programmable logic array|PLA]] (12 inputs, 50 terms, 6 outputs)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n231 SN74S330]
@@ 第2,731行： / 第2,734行： @@
 | [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs, 4 state registers)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS333]
@@ 第2,739行： / 第2,742行： @@
 | [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS334]
@@ 第2,763行： / 第2,766行： @@
 | clock driver
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n485 SN74ABT337]
@@ 第2,771行： / 第2,774行： @@
 | 8个 buffer, inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S340]
@@ 第2,779行： / 第2,782行： @@
 | 8个 buffer, non-inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S341]
@@ 第2,787行： / 第2,790行： @@
 | 8个 buffer, non-inverting outputs
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S344]
@@ 第2,803行： / 第2,806行： @@
 | 8 to 3-line priority encoder
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn74ls348 SN74LS348]
@@ 第2,811行： / 第2,814行： @@
 | 4-bit shifter
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1035 SN74S350]
@@ 第2,819行： / 第2,822行： @@
 | 2个 8-line to 1-line data selectors/multiplexers, 4 common data inputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1041 SN74351]
@@ 第2,835行： / 第2,838行： @@
 | 2个 4-line to 1-line data selectors/multiplexers, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1047 SN74LS353]
@@ 第2,843行： / 第2,846行： @@
 | 8-line to 1-line data selector/multiplexer, transparent registers
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/cd54hc354 CD74HC354]
@@ 第2,859行： / 第2,862行： @@
 | 8-line to 1-line data selector/multiplexer, edge-triggered registers
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/cd74hct356 CD74HCT356]
@@ 第2,891行： / 第2,894行： @@
 | 8个 transparent latch
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS363]
@@ 第2,899行： / 第2,902行： @@
 | 8个 edge-triggered D-type register
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS364]
@@ 第2,907行： / 第2,910行： @@
 | 6个 buffer, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn54ls366a SN74LS365A]
@@ 第2,915行： / 第2,918行： @@
 | 6个 buffer, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/ds/symlink/sn54hc366.pdf SN74HC366]
@@ 第2,923行： / 第2,926行： @@
 | 6个 buffer, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn54ls366a SN74LS367A]
@@ 第2,931行： / 第2,934行： @@
 | 6个 buffer, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn54ls366a SN74LS368A]
@@ 第2,939行： / 第2,942行： @@
 | 2048-bit [[read-only memory|ROM]] (512x4)
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S370]
@@ 第2,947行： / 第2,950行： @@
 | 2048-bit [[read-only memory|ROM]] (256x8)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S371]
@@ 第2,955行： / 第2,958行： @@
 | 8个 transparent latch
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls373 SN74LS373]
@@ 第2,963行： / 第2,966行： @@
 | 8个 register
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls373 SN74LS374]
@@ 第3,011行： / 第3,014行： @@
 | 8-bit multifunction register (combines features of x374, x377, x273, x534 ICs)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n193 SN74LS380]
@@ 第3,075行： / 第3,078行： @@
 | 4-bit D-type register
 |
-| three-state and standard
+| 三态逻辑 and standard
 | 16
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-000/Scans-0017104.pdf Am74S388]
@@ 第3,099行： / 第3,102行： @@
 | 4-bit cascadable shift register
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://web.archive.org/web/20070101063359/http://focus.ti.com/lit/ds/symlink/sn74ls395a.pdf SN74LS395A]
@@ 第3,150行： / 第3,153行： @@
 | 64-bit FIFO memory (16x4)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n383 74F403]
@@ 第3,174行： / 第3,177行： @@
 | data access register
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n401 74F407]
@@ 第3,206行： / 第3,209行： @@
 | 64-bit RAM (16x4) with output register
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n407 74F410]
@@ 第3,222行： / 第3,225行： @@
 | multi-mode buffered 8-bit latches (equivalent to Intel [[Intel 3000|3212]]/8212)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n247 SN74S412]
@@ 第3,254行： / 第3,257行： @@
 | 4-bit bidirectional bus transceiver, non-inverting (equivalent to Intel 8216)
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://pdf.datasheetcatalog.com/datasheet/CEMI/mXyztyxq.pdf UCY74S416]
@@ 第3,278行： / 第3,281行： @@
 | 32-bit error detection and correction circuit
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n375 74F418]
@@ 第3,302行： / 第3,305行： @@
 | 32-bit check bit / syndrome bit generator
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n421 74F420]
@@ 第3,334行： / 第3,337行： @@
 | 4个 bus buffers, active low enables
 |
-| three-state
+| 三态逻辑
 | 14
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1139 SN74425]
@@ 第3,342行： / 第3,345行： @@
 | 4个 bus buffers, active high enables
 |
-| three-state
+| 三态逻辑
 | 14
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1139 SN74426]
@@ 第3,358行： / 第3,361行： @@
 | FIFO RAM controller
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0037196.pdf 74LS429]
@@ 第3,374行： / 第3,377行： @@
 | 8-bit multi-mode buffered latch
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n425 74F432]
@@ 第3,382行： / 第3,385行： @@
 | 256-bit FIFO memory (64x4)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n431 74F433]
@@ 第3,430行： / 第3,433行： @@
 | 4个 tridirectional bus transceiver, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20070102044619/http://focus.ti.com/lit/ds/symlink/sn74ls442.pdf SN74LS442]
@@ 第3,438行： / 第3,441行： @@
 | 4个 tridirectional bus transceiver, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1147 SN74LS443]
@@ 第3,446行： / 第3,449行： @@
 | 4个 tridirectional bus transceiver, inverting and non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20070102044619/http://focus.ti.com/lit/ds/symlink/sn74ls442.pdf SN74LS444]
@@ 第3,462行： / 第3,465行： @@
 | 4个 bus transceivers, direction controls, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1155 SN74LS446]
@@ 第3,486行： / 第3,489行： @@
 | 4个 bus transceivers, direction controls, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1155 SN74LS449]
@@ 第3,502行： / 第3,505行： @@
 | 8192-bit PROM (1024x8) with power-down
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S450]
@@ 第3,574行： / 第3,577行： @@
 | 8个 buffer / line driver with parity, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n505 74F455]
@@ 第3,590行： / 第3,593行： @@
 | 8个 buffer / line driver with parity, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n505 74F456]
@@ 第3,606行： / 第3,609行： @@
 | 4-bit bus transfer switch
 | {{Unknown|{{?}}}}
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n423 MC74460]
@@ 第3,622行： / 第3,625行： @@
 | 8-bit presettable binary counter
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n185 SN74LS461]
@@ 第3,646行： / 第3,649行： @@
 | 8个 buffer, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS465]
@@ 第3,654行： / 第3,657行： @@
 | 8个 buffers, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS466]
@@ 第3,662行： / 第3,665行： @@
 | 8个 buffers, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS467]
@@ 第3,670行： / 第3,673行： @@
 | 8个 buffers, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS468]
@@ 第3,678行： / 第3,681行： @@
 | 8-bit synchronous up/down counter, parallel load and hold capability
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n191 SN74LS469]
@@ 第3,694行： / 第3,697行： @@
 | 2048-bit [[programmable read-only memory|PROM]] (256x8)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S471]
@@ 第3,702行： / 第3,705行： @@
 | 4096-bit [[programmable read-only memory|PROM]] (512x8)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S472]
@@ 第3,718行： / 第3,721行： @@
 | 4096-bit [[programmable read-only memory|PROM]] (512x8)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S474]
@@ 第3,734行： / 第3,737行： @@
 | 4096-bit [[programmable read-only memory|PROM]] (1024x4)
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S476]
@@ 第3,750行： / 第3,753行： @@
 | 8192-bit [[programmable read-only memory|PROM]] (1024x8)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S478]
@@ 第3,790行： / 第3,793行： @@
 | BCD-to-binary converter
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBook1986_14886851/page/n379 SN74S484A]
@@ 第3,798行： / 第3,801行： @@
 | binary-to-BCD converter
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBook1986_14886851/page/n379 SN74S485A]
@@ 第3,822行： / 第3,825行： @@
 | 10-bit binary up/down counter, limited preset
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n197 SN74LS491]
@@ 第3,830行： / 第3,833行： @@
 | 8-bit bidirectional shift register, parallel inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n189 SN74LS498]
@@ 第3,873行： / 第3,876行： @@
 | 8-bit [[successive approximation ADC]]
 | analog
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n413 74F505]
@@ 第3,985行： / 第3,988行： @@
 | 8个 transparent latch
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n329 SN74S531]
@@ 第3,993行： / 第3,996行： @@
 | 8个 register
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n329 SN74S532]
@@ 第4,001行： / 第4,004行： @@
 | 8个 transparent latch, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/cd74hct563 CD74HC533]
@@ 第4,009行： / 第4,012行： @@
 | 8个 register, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/cd74hc564 CD74HC534]
@@ 第4,017行： / 第4,020行： @@
 | 8个 transparent latch, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n331 SN74S535]
@@ 第4,025行： / 第4,028行： @@
 | 8个 register, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n331 SN74S536]
@@ 第4,033行： / 第4,036行： @@
 | BCD to decimal decoder
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n247 MC74F537]
@@ 第4,041行： / 第4,044行： @@
 | 3-to-8 line decoder/demultiplexer
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n389 SN74ALS538]
@@ 第4,049行： / 第4,052行： @@
 | 2个 2-to-4 line decoder/demultiplexer
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n393 SN74ALS539]
@@ 第4,057行： / 第4,060行： @@
 | 8个 非门
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls540 SN74LS540]
@@ 第4,065行： / 第4,068行： @@
 | 8个 buffer gate
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54ls540 SN74LS541]
@@ 第4,073行： / 第4,076行： @@
 | 8个 registered transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74f543 SN74F543]
@@ 第4,081行： / 第4,084行： @@
 | 8个 registered transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n261 MC74F544]
@@ 第4,089行： / 第4,092行： @@
 | 8个 bidirectional transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n497 74F545]
@@ 第4,097行： / 第4,100行： @@
 | 8-bit bidirectional registered transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS546]
@@ 第4,105行： / 第4,108行： @@
 | 8-bit bidirectional latched transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS547]
@@ 第4,121行： / 第4,124行： @@
 | 8-bit two-stage pipelined register
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n637 SN74LS548]
@@ 第4,137行： / 第4,140行： @@
 | 8-bit two-stage pipelined latch
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n637 SN74LS549]
@@ 第4,145行： / 第4,148行： @@
 | 8个 registered transceiver with status flags, non-inverting
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n509 74F550]
@@ 第4,153行： / 第4,156行： @@
 | 8个 registered transceiver with status flags, inverting
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n509 74F551]
@@ 第4,161行： / 第4,164行： @@
 | 8个 registered transceiver with parity and flags
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n515 74F552]
@@ 第4,169行： / 第4,172行： @@
 | 16x16-bit multiplier slice
 |
-| three-state
+| 三态逻辑
 | (84)
 | [https://archive.org/details/bitsavers_mmidataBook7ed_126879625/page/n567 74S556]
@@ 第4,177行： / 第4,180行： @@
 | 8-bit by 8-bit multiplier
 |
-| three-state
+| 三态逻辑
 | 40
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n381 SN74S557]
@@ 第4,185行： / 第4,188行： @@
 | 8-bit by 8-bit multiplier
 |
-| three-state
+| 三态逻辑
 | 40
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n381 SN74S558]
@@ 第4,193行： / 第4,196行： @@
 | 8-bit expandable two's complement multiplier/divider
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_20099339/page/n311 74F559]
@@ 第4,201行： / 第4,204行： @@
 | 4-bit decade counter
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n401 SN74ALS560A]
@@ 第4,209行： / 第4,212行： @@
 | 4-bit binary counter
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20170305192612/http://www.ti.com/lit/ds/symlink/sn74als561a.pdf SN74ALS561A]
@@ 第4,217行： / 第4,220行： @@
 | 8-bit D-type transparent latch, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54als563b SN74ALS563B]
@@ 第4,225行： / 第4,228行： @@
 | 8-bit D-type edge-triggered register, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn54als564b SN74ALS564B]
@@ 第4,233行： / 第4,236行： @@
 | 8-bit bidirectional registered transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS566]
@@ 第4,241行： / 第4,244行： @@
 | 8-bit bidirectional latched transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS567]
@@ 第4,249行： / 第4,252行： @@
 | decade up/down counter
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als569a SN74ALS568A]
@@ 第4,257行： / 第4,260行： @@
 | binary up/down counter
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als569a SN74ALS569A]
@@ 第4,273行： / 第4,276行： @@
 | 2048-bit PROM (512x4)
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_nationaldataBook_16727669/page/n315 DM74S571]
@@ 第4,289行： / 第4,292行： @@
 | 8个 D-type transparent latch
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als573c SN74ALS573C]
@@ 第4,297行： / 第4,300行： @@
 | 8个 D-type edge-triggered flip-flop
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/ds/symlink/sn74hc574.pdf SN74HC574]
@@ 第4,305行： / 第4,308行： @@
 | 8个 D-type edge-triggered flip-flop, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als575a SN74ALS575A]
@@ 第4,313行： / 第4,316行： @@
 | 8个 D-type edge-triggered flip-flop, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74as576 SN74ALS576B]
@@ 第4,321行： / 第4,324行： @@
 | 8个 D-type edge-triggered flip-flop, synchronous clear, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74as576 SN74ALS577A]
@@ 第4,329行： / 第4,332行： @@
 | 8-bit bidirectional binary counter
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n273 MC74F579]
@@ 第4,337行： / 第4,340行： @@
 | 8个 D-type transparent latch, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als580b SN74ALS580B]
@@ 第4,361行： / 第4,364行： @@
 | 8个 bidirectional transceiver with [[IEEE-488]] termination resistors
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n559 74F588]
@@ 第4,369行： / 第4,372行： @@
 | 8-bit shift register, input latch
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1181 SN74LS589]
@@ 第4,377行： / 第4,380行： @@
 | 8-bit binary counter, output registers
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn74ls590 SN74LS590]
@@ 第4,401行： / 第4,404行： @@
 | 8-bit binary counter, input registers
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls592 SN74LS593]
@@ 第4,417行： / 第4,420行： @@
 | 8-bit shift registers, Serial-In, Parallel-Out, output latches, output enable
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn74ls595 SN74LS595]
@@ 第4,441行： / 第4,444行： @@
 | 8-bit shift register, Selectable Parallel-In/Out input latches
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls597 SN74LS598]
@@ 第4,460行： / 第4,463行： @@
 | dynamic memory refresh controller, transparent and burst modes, for 4K or 16K dRAM
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS600A]
@@ 第4,468行： / 第4,471行： @@
 | dynamic memory refresh controller, transparent and burst modes, for 64K dRAM
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS601A]
@@ 第4,476行： / 第4,479行： @@
 | dynamic memory refresh controller, cycle steal and burst modes, for 4K or 16K dRAM
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS602A]
@@ 第4,484行： / 第4,487行： @@
 | dynamic memory refresh controller, cycle steal and burst modes, for 64K dRAM
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS603A]
@@ 第4,492行： / 第4,495行： @@
 | 8个 2输入 multiplexer, latch, high-speed
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1225 SN74LS604]
@@ 第4,508行： / 第4,511行： @@
 | 8个 2输入 multiplexer, latch, glitch-free
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1225 SN74LS606]
@@ 第4,532行： / 第4,535行： @@
 | memory mapper, latched
 |
-| three-state
+| 三态逻辑
 | 40
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1237 SN74LS610]
@@ 第4,548行： / 第4,551行： @@
 | memory mapper
 |
-| three-state
+| 三态逻辑
 | 40
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1237 SN74LS612]
@@ 第4,580行： / 第4,583行： @@
 | 16-bit parallel error detection and correction
 |
-| three-state
+| 三态逻辑
 | 40
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n101 SN74ALS616]
@@ 第4,596行： / 第4,599行： @@
 | 8个 bus transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls623 SN74LS620]
@@ 第4,620行： / 第4,623行： @@
 | 8个 bus transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls623 SN74LS623]
@@ 第4,676行： / 第4,679行： @@
 | 16-bit error detection and correction (EDAC)
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1263 SN74LS630]
@@ 第4,692行： / 第4,695行： @@
 | 32-bit parallel error detection and correction, byte-write
 |
-| three-state
+| 三态逻辑
 | 52
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n457 SN74ALS632]
@@ 第4,708行： / 第4,711行： @@
 | 32-bit parallel error detection and correction
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n457 SN74ALS634]
@@ 第4,724行： / 第4,727行： @@
 | 8-bit parallel error detection and correction
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1271 SN74LS636]
@@ 第4,740行： / 第4,743行： @@
 | 8个 bus transceiver, inverting outputs
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1279 SN74LS638]
@@ 第4,748行： / 第4,751行： @@
 | 8个 bus transceiver, non-inverting outputs
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1279 SN74LS639]
@@ 第4,756行： / 第4,759行： @@
 | 8个 bus transceiver, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls640 SN74LS640]
@@ 第4,780行： / 第4,783行： @@
 | 8个 bus transceiver, mix of inverting and non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1283 SN74LS643]
@@ 第4,796行： / 第4,799行： @@
 | 8个 bus transceiver, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls640 SN74LS645]
@@ 第4,804行： / 第4,807行： @@
 | 8个 bus transceiver/latch/multiplexer, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn54als648 SN74ALS646A]
@@ 第4,820行： / 第4,823行： @@
 | 8个 bus transceiver/latch/multiplexer, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn54als648 SN74ALS648A]
@@ 第4,836行： / 第4,839行： @@
 | 8个 bus transceiver/register, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als654 SN74ALS651A]
@@ 第4,844行： / 第4,847行： @@
 | 8个 bus transceiver/register, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als654 SN74ALS652A]
@@ 第4,852行： / 第4,855行： @@
 | 8个 bus transceiver/register, inverting outputs
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 24
 | [http://www.ti.com/lit/gpn/sn74als654 SN74ALS653]
@@ 第4,860行： / 第4,863行： @@
 | 8个 bus transceiver/register, non-inverting outputs
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 24
 | [http://www.ti.com/lit/gpn/sn74als654 SN74ALS654]
@@ 第4,868行： / 第4,871行： @@
 | 8个 buffer / line driver with parity, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n553 74F655]
@@ 第4,876行： / 第4,879行： @@
 | 8个 buffer / line driver with parity, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n553 74F656]
@@ 第4,884行： / 第4,887行： @@
 | 8个 bidirectional transceiver with 8-bit parity generator/checker
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74f657 SN74F657]
@@ 第4,892行： / 第4,895行： @@
 | 8个 bus transceiver, parity, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n395 SN74HC658]
@@ 第4,900行： / 第4,903行： @@
 | 8个 bus transceiver, parity, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n395 SN74HC659]
@@ 第4,908行： / 第4,911行： @@
 | 8个 bus transceiver, parity, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n409 SN74HC664]
@@ 第4,916行： / 第4,919行： @@
 | 8个 bus transceiver, parity, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n409 SN74HC665]
@@ 第4,924行： / 第4,927行： @@
 | 8-bit D-type transparent read-back latch, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als666 SN74ALS666]
@@ 第4,932行： / 第4,935行： @@
 | 8-bit D-type transparent read-back latch, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als666 SN74ALS667]
@@ 第4,956行： / 第4,959行： @@
 | 16-bit register file (4x4)
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/sn54ls670 SN74LS670]
@@ 第4,964行： / 第4,967行： @@
 | 4-bit bidirectional shift register/latch/multiplexer, direct clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1327 SN74LS671]
@@ 第4,972行： / 第4,975行： @@
 | 4-bit bidirectional shift register/latch/multiplexer, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1327 SN74LS672]
@@ 第4,980行： / 第4,983行： @@
 | 16-bit serial-in, serial/parallel-out shift register, output storage registers
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74ls673 SN74LS673]
@@ 第4,988行： / 第4,991行： @@
 | 16-bit parallel-in, serial-out shift register
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74ls673 SN74LS674]
@@ 第5,044行： / 第5,047行： @@
 | 4-bit parallel binary accumulator
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1339 SN74LS681]
@@ 第5,116行： / 第5,119行： @@
 | 4-bit decimal counter/latch/multiplexer, asynchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS690]
@@ 第5,124行： / 第5,127行： @@
 | 4-bit binary counter/latch/multiplexer, asynchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS691]
@@ 第5,132行： / 第5,135行： @@
 | 4-bit decimal counter/latch/multiplexer, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS692]
@@ 第5,140行： / 第5,143行： @@
 | 4-bit binary counter/latch/multiplexer, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS693]
@@ 第5,148行： / 第5,151行： @@
 | 4-bit decimal counter/latch/multiplexer,  synchronous and asynchronous clears
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_icMaster19_159569496/page/n619 SN74ALS694]
@@ 第5,156行： / 第5,159行： @@
 | 4-bit binary counter/latch/multiplexer, synchronous and asynchronous clears
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_icMaster19_159569496/page/n619 SN74ALS695]
@@ 第5,164行： / 第5,167行： @@
 | 4-bit decimal counter/register/multiplexer, asynchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls697 SN74LS696]
@@ 第5,172行： / 第5,175行： @@
 | 4-bit binary counter/register/multiplexer, asynchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls697 SN74LS697]
@@ 第5,180行： / 第5,183行： @@
 | 4-bit decimal counter/register/multiplexer, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1365 SN74LS698]
@@ 第5,188行： / 第5,191行： @@
 | 4-bit binary counter/register/multiplexer, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74ls697 SN74LS699]
@@ 第5,199行： / 第5,202行： @@
 | 8个 dRAM driver, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S700]
@@ 第5,207行： / 第5,210行： @@
 | 8-bit register/counter/comparator
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n615 74F701]
@@ 第5,215行： / 第5,218行： @@
 | 8-bit registered read-back transceiver
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n617 74F702]
@@ 第5,223行： / 第5,226行： @@
 | arithmetic logic unit for digital signal processing applications
 |
-| three-state
+| 三态逻辑
 | (84)
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n349 74ACT705]
@@ 第5,239行： / 第5,242行： @@
 | 576-bit FIFO memory (64x9)
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n361 74ACT708]
@@ 第5,255行： / 第5,258行： @@
 | quint 2-to-1 multiplexers
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n777 74F711]
@@ 第5,295行： / 第5,298行： @@
 | 576-bit FIFO memory (64x9)
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n379 74ACT723]
@@ 第5,311行： / 第5,314行： @@
 | 4608-bit FIFO memory (512x9)
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n395 74ACT725]
@@ 第5,319行： / 第5,322行： @@
 | 8个 dRAM driver, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S730]
@@ 第5,327行： / 第5,330行： @@
 | 8个 dRAM driver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S731]
@@ 第5,335行： / 第5,338行： @@
 | 4-bit 3-bus multiplexer, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n789 74F732]
@@ 第5,343行： / 第5,346行： @@
 | 4-bit 3-bus multiplexer, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n789 74F733]
@@ 第5,351行： / 第5,354行： @@
 | 8个 dRAM driver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S734]
@@ 第5,359行： / 第5,362行： @@
 | 2个 4-bit line driver, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137088.pdf SN74S740]
@@ 第5,367行： / 第5,370行： @@
 | 2个 4-bit line driver, non-inverting, complementary enable inputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137088.pdf SN74S741]
@@ 第5,391行： / 第5,394行： @@
 | 2个 4-bit line driver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137088.pdf SN74S744]
@@ 第5,399行： / 第5,402行： @@
 | 8个 buffer / line driver, inverting
 | 20&nbsp;kΩ pull-up
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n623 SN74ALS746]
@@ 第5,407行： / 第5,410行： @@
 | 8个 buffer / line driver, non-inverting
 | 20&nbsp;kΩ pull-up
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n623 SN74ALS747]
@@ 第5,495行： / 第5,498行： @@
 | 8-bit latched transceiver for [[FutureBus]]
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 28
 | [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n453 SN74F776]
@@ 第5,503行： / 第5,506行： @@
 | 3个 latched transceiver
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 20
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F777_PhilipsSemiconductors.pdf 74F777]
@@ 第5,511行： / 第5,514行： @@
 | 8-bit bidirectional binary counter
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n297 MC74F779]
@@ 第5,551行： / 第5,554行： @@
 | error detection and correction (EDAC)
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n629 SN74ALS790]
@@ 第5,575行： / 第5,578行： @@
 | 8个 buffer, non-inverting, common enable
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS795]
@@ 第5,583行： / 第5,586行： @@
 | 8个 buffer, inverting, common enable
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS796]
@@ 第5,591行： / 第5,594行： @@
 | 8个 buffer, non-inverting, enable for 4 buffers each
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS797]
@@ 第5,599行： / 第5,602行： @@
 | 8个 buffer, inverting, enable for 4 buffers each
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS798]
@@ 第5,682行： / 第5,685行： @@
 | 8-bit diagnostic register
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n411 74ACT818]
@@ 第5,690行： / 第5,693行： @@
 | 8-bit diagnostic / pipeline register
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://pdf1.alldatasheet.com/datasheet-pdf/view/466541/TI1/SN74ALS819.html SN74ALS819]
@@ 第5,698行： / 第5,701行： @@
 | 10-bit bus interface flip-flop
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn54as821a SN74AS821A]
@@ 第5,706行： / 第5,709行： @@
 | 10-bit bus interface flip-flop, inverting inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n557 SN74AS822]
@@ 第5,714行： / 第5,717行： @@
 | 9-bit D-type flip-flops, clear and clock enable inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn54as823a SN74AS823A]
@@ 第5,722行： / 第5,725行： @@
 | 9-bit D-type flip-flops, clear and clock enable inputs, inverting inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n563 SN74AS824]
@@ 第5,730行： / 第5,733行： @@
 | 8-bit D-type flip-flop, clear and clock enable inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn54as825a SN74AS825A]
@@ 第5,738行： / 第5,741行： @@
 | 8-bit D-type flip-flop, clear and clock enable inputs, inverting inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n569 SN74AS826]
@@ 第5,746行： / 第5,749行： @@
 | 10-bit buffer, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n303 MC74F827]
@@ 第5,754行： / 第5,757行： @@
 | 10-bit buffer, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n303 MC74F828]
@@ 第5,770行： / 第5,773行： @@
 | 8-bit to 9-bit bus transceiver with parity register, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74abt833 SN74ABT833]
@@ 第5,778行： / 第5,781行： @@
 | 8-bit to 9-bit bus transceiver with parity register, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_idtdataBoomanceCMOSDataBook_66222191/page/n1071 IDT74FCT834]
@@ 第5,794行： / 第5,797行： @@
 | field-programmable logic array 14x32x6
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/TexasInstruments-TI-Data-TtlDataBookVol1_1984-DL/page/n259 SN74PL839]
@@ 第5,810行： / 第5,813行： @@
 | 10-bit D-type flip-flop
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://web.archive.org/web/20170225141931/http://www.ti.com/lit/ds/symlink/sn74als841.pdf SN74ALS841]
@@ 第5,818行： / 第5,821行： @@
 | 10-bit D-type flip-flop, inverting inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n579 SN74ALS842]
@@ 第5,826行： / 第5,829行： @@
 | 9-bit D flip-flops, clear and set inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als843 SN74ALS843]
@@ 第5,834行： / 第5,837行： @@
 | 9-bit D flip-flops, clear and set inputs, inverting inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n587 SN74ALS844]
@@ 第5,842行： / 第5,845行： @@
 | 8-bit D flip-flops, clear and set inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n595 SN74ALS845]
@@ 第5,850行： / 第5,853行： @@
 | 8-bit D flip-flops, clear and set inputs, inverting inputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n595 SN74ALS846]
@@ 第5,858行： / 第5,861行： @@
 | 8 to 3-line priority encoder (glitch-less)
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n315 SN74LS848]
@@ 第5,866行： / 第5,869行： @@
 | 1 of 16 data selector/multiplexer, clocked select
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n603 SN74AS850]
@@ 第5,874行： / 第5,877行： @@
 | 1 of 16 data selector/multiplexer
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n603 SN74AS851]
@@ 第5,882行： / 第5,885行： @@
 | 8-bit universal transceiver port controller
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n613 SN74AS852]
@@ 第5,890行： / 第5,893行： @@
 | 8-bit to 9-bit bus transceiver with parity latch, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74abt853 SN74ABT853]
@@ 第5,898行： / 第5,901行： @@
 | 8-bit to 9-bit bus transceiver with parity latch, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_idtdataBoomanceCMOSDataBook_66222191/page/n1071 IDT74FCT854]
@@ 第5,906行： / 第5,909行： @@
 | 8-bit universal transceiver port controller
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n619 SN74AS856]
@@ 第5,914行： / 第5,917行： @@
 | 6个 2-line to 1-line multiplexer
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn54als857 SN74ALS857]
@@ 第5,922行： / 第5,925行： @@
 | 10-bit bus transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBook_80793740/page/n263 SN74ABT861]
@@ 第5,930行： / 第5,933行： @@
 | 10-bit bus transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBook_80793740/page/n269 SN74ABT862]
@@ 第5,938行： / 第5,941行： @@
 | 9-bit bus transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBook_80793740/page/n273 SN74ABT863]
@@ 第5,946行： / 第5,949行： @@
 | 9-bit bus transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n867 74F864]
@@ 第5,994行： / 第5,997行： @@
 | 2个 4-bit transparent latch with clear
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als873b SN74ALS873B]
@@ 第6,002行： / 第6,005行： @@
 | 2个 4-bit edge-triggered D flip-flops with clear
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74as874 SN74ALS874]
@@ 第6,010行： / 第6,013行： @@
 | 2个 4-bit edge-triggered D flip-flops with set, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74as874 SN74ALS876]
@@ 第6,018行： / 第6,021行： @@
 | 8-bit universal transceiver port controller
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n663 SN74AS877]
@@ 第6,026行： / 第6,029行： @@
 | 2个 4-bit D-type flip-flop, synchronous clear, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n669 SN74ALS878]
@@ 第6,034行： / 第6,037行： @@
 | 2个 4-bit D-type flip-flop, synchronous clear, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n669 SN74ALS879]
@@ 第6,042行： / 第6,045行： @@
 | 2个 4-bit transparent latch with clear, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n675 SN74ALS880]
@@ 第6,130行： / 第6,133行： @@
 | 9-bit latchable transceiver with parity generator / checker
 |
-| three-state
+| 三态逻辑
 | (28)
 | [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n431 74AC899]
@@ 第6,237行： / 第6,240行： @@
 | 256-bit RAM (64x4)
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n115 MM74C910]
@@ 第6,245行： / 第6,248行： @@
 | 4-digit expandable display controller
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n135 MM74C911]
@@ 第6,253行： / 第6,256行： @@
 | 6-digit BCD display controller and driver
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n135 MM74C912]
@@ 第6,277行： / 第6,280行： @@
 | 7-segment to BCD converter
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n141 MM74C915]
@@ 第6,285行： / 第6,288行： @@
 | 6-digit 6个 display controller and driver
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1333 MM74C917]
@@ 第6,301行： / 第6,304行： @@
 | 1024-bit RAM (256x4), separate data inputs and outputs
 |
-| three-state
+| 三态逻辑
 | 22
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n145 MM74C920]
@@ 第6,309行： / 第6,312行： @@
 | 1024-bit RAM (256x4)
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n145 MM74C921]
@@ 第6,317行： / 第6,320行： @@
 | 16-key encoder
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n149 MM74C922]
@@ 第6,325行： / 第6,328行： @@
 | 20-key encoder
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n149 MM74C923]
@@ 第6,365行： / 第6,368行： @@
 | 1024-bit RAM (1024x1), single chip select
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C929]
@@ 第6,373行： / 第6,376行： @@
 | 1024-bit RAM (1024x1), three chip selects
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C930]
@@ 第6,437行： / 第6,440行： @@
 | 8个 bus/line drivers/line receivers
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n161 DM74S940]
@@ 第6,445行： / 第6,448行： @@
 | 8个 bus/line drivers/line receivers
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n161 DM74S941]
@@ 第6,493行： / 第6,496行： @@
 | 8-bit [[Analog-to-digital converter|ADC]] with 16-channel analog multiplexer
 | analog
-| three-state
+| 三态逻辑
 | 40
 | [https://archive.org/details/bitsavers_nationaldaDataAcquisitionHandbook_38492992/page/n63 MM74C948]
@@ 第6,501行： / 第6,504行： @@
 | 8-bit [[Analog-to-digital converter|ADC]] with 8-channel analog multiplexer
 | analog
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/n173 MM74C949]
@@ 第6,509行： / 第6,512行： @@
 | 8-bit [[Analog-to-digital converter|ADC]] with 8-channel analog multiplexer and [[sample and hold]]
 | analog
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/n173 MM74C950]
@@ 第6,517行： / 第6,520行： @@
 | 2个 rank 8-bit shift register, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n417 DM74LS952]
@@ 第6,533行： / 第6,536行： @@
 | 8个 bus transceiver and latch
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheetspdf.com/pdf-file/1271601/Texas/SN74BCT956/1 SN74BCT956]
@@ 第6,541行： / 第6,544行： @@
 | 2个 rank 8-bit shift register, register exchange mode
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n417 DM74LS962]
@@ 第6,549行： / 第6,552行： @@
 | 2个 rank 8-bit shift register, synchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n461 SN74ALS963]
@@ 第6,557行： / 第6,560行： @@
 | 2个 rank 8-bit shift register, synchronous and asynchronous clear
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n461 SN74ALS964]
@@ 第6,581行： / 第6,584行： @@
 | 9-bit registered transceiver with parity generator/checker for [[FutureBus]]
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (48)
 | [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n447 SN74BCT979]
@@ 第6,589行： / 第6,592行： @@
 | 64-bit RAM (64x4), inverting output
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1313 MM74C989]
@@ 第6,597行： / 第6,600行： @@
 | 8-bit D-type transparent read-back latch, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als990 SN74ALS990]
@@ 第6,605行： / 第6,608行： @@
 | 8-bit D-type transparent read-back latch, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n473 SN74ALS991]
@@ 第6,613行： / 第6,616行： @@
 | 9-bit D-type transparent read-back latch, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als992 SN74ALS992]
@@ 第6,621行： / 第6,624行： @@
 | 9-bit D-type transparent read-back latch, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n481 SN74ALS993]
@@ 第6,629行： / 第6,632行： @@
 | 10-bit D-type transparent read-back latch, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n489 SN74ALS994]
@@ 第6,637行： / 第6,640行： @@
 | 10-bit D-type transparent read-back latch, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n489 SN74ALS995]
@@ 第6,645行： / 第6,648行： @@
 | 8-bit D-type edge-triggered read-back latch
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74als996 SN74ALS996]
@@ 第6,712行： / 第6,715行： @@
 | 16x16-bit multiplier/accumulator
 |
-| three-state
+| 三态逻辑
 | 64
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n457 74AC1010]
@@ 第6,736行： / 第6,739行： @@
 | 16x16-bit multiplier
 |
-| three-state
+| 三态逻辑
 | 64
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n467 74AC1016]
@@ 第6,744行： / 第6,747行： @@
 | 16x16-bit parallel multiplier
 |
-| three-state
+| 三态逻辑
 | 64
 | [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n479 74AC1017]
@@ 第6,872行： / 第6,875行： @@
 | 8个 buffer / line driver, inverting (lower-power version of 74x240)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n731 SN74ALS1240]
@@ 第6,880行： / 第6,883行： @@
 | 8个 buffer / line driver, non-inverting (lower-power version of 74x241)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n731 SN74ALS1241]
@@ 第6,888行： / 第6,891行： @@
 | 4个 bus transceiver, inverting (lower-power version of 74x242)
 |
-| three-state
+| 三态逻辑
 | 14
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n735 SN74ALS1242]
@@ 第6,896行： / 第6,899行： @@
 | 4个 bus transceiver, non-inverting (lower-power version of 74x243)
 |
-| three-state
+| 三态逻辑
 | 14
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n735 SN74ALS1243]
@@ 第6,904行： / 第6,907行： @@
 | 8个 buffer / driver, non-inverting (lower-power version of 74x244)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n739 SN74ALS1244]
@@ 第6,912行： / 第6,915行： @@
 | 8个 bus transceiver (lower-power version of 74x245)
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als1245a SN74ALS1245A]
@@ 第6,920行： / 第6,923行： @@
 | 9-bit parity generator/checker with registered outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://web.archive.org/web/20181117162114/https://4donline.ihs.com/images/VipMasterIC/IC/QSEM/QSEMD004/QSEMD004-3-71.pdf QS74FCT1280]
@@ 第6,936行： / 第6,939行： @@
 | 8-bit bus receiver plus 4-bit bus driver
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | (32)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-25/DSA-497532.pdf 74LVT1403]
@@ 第6,960行： / 第6,963行： @@
 | 16x16-bit multimode multiplier
 |
-| three-state
+| 三态逻辑
 | 64
 | [https://archive.org/details/bitsavers_icMaster19_159569496/page/n919 SN74ALS1616]
@@ 第6,968行： / 第6,971行： @@
 | 8个 bus transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n747 SN74ALS1620]
@@ 第6,992行： / 第6,995行： @@
 | 8个 bus transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n747 SN74ALS1623]
@@ 第7,000行： / 第7,003行： @@
 | 4个 bus driver with complementary outputs
 |
-| three-state
+| 三态逻辑
 | 16
 | SN74ALS1631<ref name=ttltb3/>{{rp|at=3-336}}
@@ 第7,008行： / 第7,011行： @@
 | 8个 bus transceiver, inverting (lower-power version of 74x638)
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n753 SN74ALS1638]
@@ 第7,016行： / 第7,019行： @@
 | 8个 bus transceiver, non-inverting (lower-power version of 74x639)
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n753 SN74ALS1639]
@@ 第7,024行： / 第7,027行： @@
 | 8个 bus transceiver, inverting (lower-power version of 74x640)
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als1645a SN74ALS1640A]
@@ 第7,048行： / 第7,051行： @@
 | 8个 bus transceiver, inverting and non-inverting (lower-power version of 74x643)
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n757 SN74ALS643]
@@ 第7,064行： / 第7,067行： @@
 | 8个 bus transceiver, non-inverting (lower-power version of 74x645)
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74als1645a SN74ALS1645A]
@@ 第7,072行： / 第7,075行： @@
 | 2个 9-bit [[Futurebus]] universal storage transceiver with split TTL I/O
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (100)
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n689 SN74FB1650]
@@ 第7,080行： / 第7,083行： @@
 | 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split TTL I/O
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (100)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-703111.pdf SN74FB1651]
@@ 第7,088行： / 第7,091行： @@
 | 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split 3.3V TTL I/O
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (100)
 | [http://www.ti.com/lit/gpn/SN74FB1653 SN74FB1653]
@@ 第7,096行： / 第7,099行： @@
 | 2个 8-bit [[Gunning transceiver logic|GTL]] universal storage transceivers with live insertion
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (64)
 | [http://www.ti.com/lit/gpn/SN74GTL1655 SN74GTL1655]
@@ 第7,104行： / 第7,107行： @@
 | 10-bit 4-way latched address multiplexer
 |
-| three-state
+| 三态逻辑
 | 64
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0034403.pdf 74F1760]
@@ 第7,160行： / 第7,163行： @@
 | 8-bit bidirectional binary counter
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F1779_PhilipsSemiconductors.pdf 74F1779]
@@ 第7,176行： / 第7,179行： @@
 | [[SerDes]] with [[Error correction code|ECC]] and [[Cyclic redundancy check|CRC]], data rates up to 10&nbsp;MHz
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://4donline.ihs.com/images/VipMasterIC/IC/SIGC/SIGCD005/SIGCD005-7-26.pdf 74LS1802]
@@ 第7,224行： / 第7,227行： @@
 | [[SerDes]] with [[Error correction code|ECC]] and [[Cyclic redundancy check|CRC]], data rates up to 30&nbsp;MHz
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://4donline.ihs.com/images/VipMasterIC/IC/SIGC/SIGCD005/SIGCD005-7-37.pdf 74LS1812]
@@ 第7,232行： / 第7,235行： @@
 | 10-bit bus interface flip-flops
 |
-| three-state
+| 三态逻辑
 | 24
 | [http://www.elektronikjk.pl/elementy_czynne/IC/SN74AS1821.pdf SN74AS1821]
@@ 第7,240行： / 第7,243行： @@
 | 9-bit bus interface flip-flops with clear
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00218035.pdf SN74AS1823]
@@ 第7,256行： / 第7,259行： @@
 | 10-bit bus interface transparent latches
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00218036.pdf SN74AS1841]
@@ 第7,264行： / 第7,267行： @@
 | 9-bit bus interface transparent latches with clear
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-706295.pdf SN74AS1843]
@@ 第7,275行： / 第7,278行： @@
 | direction discriminator with microprocessor interface
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-110/22.pdf SN74LS2000]
@@ 第7,315行： / 第7,318行： @@
 | 4-bit [[Gunning transceiver logic|GTL]] to TTL transceiver
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (14)
 | [http://www.ti.com/lit/gpn/SN74GTL2014 SN74GTL2014]
@@ 第7,323行： / 第7,326行： @@
 | 9-bit [[Futurebus]] address/data transceiver
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (48)
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n695 SN74FB2031]
@@ 第7,331行： / 第7,334行： @@
 | 9-bit [[Futurebus]] competition transceiver
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (48)
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n701 SN74FB2032]
@@ 第7,339行： / 第7,342行： @@
 | 8-bit [[Futurebus]] registered transceiver with split TTL I/O
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (52)
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n709 SN74FB2033]
@@ 第7,347行： / 第7,350行： @@
 | 8-bit [[Futurebus]] transceiver with split TTL I/O
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (48)
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n719 SN74FB2040]
@@ 第7,355行： / 第7,358行： @@
 | 7-bit [[Futurebus]] transceiver with split TTL I/O
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (52)
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n725 SN74FB2041]
@@ 第7,371行： / 第7,374行： @@
 | 4个 bus buffer
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | (14)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-2/DSA-33230.pdf TC74VCX2125]
@@ 第7,379行： / 第7,382行： @@
 | 8k x 18 cache data RAM
 |
-| three-state
+| 三态逻辑
 | (52)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2140A]
@@ 第7,443行： / 第7,446行： @@
 | 2k x 8 burst cache address comparator
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2155]
@@ 第7,451行： / 第7,454行： @@
 | 16k x 4 burst cache address comparator
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2156]
@@ 第7,459行： / 第7,462行： @@
 | 2k x 16 cache address comparator
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2157]
@@ 第7,475行： / 第7,478行： @@
 | 8k x 9 cache address comparator
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2158]
@@ 第7,483行： / 第7,486行： @@
 | 8k x 9 cache address comparator
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2159]
@@ 第7,491行： / 第7,494行： @@
 | 8k x 4 2-way cache address comparator
 |
-| three-state
+| 三态逻辑
 | (32)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2160]
@@ 第7,507行： / 第7,510行： @@
 | 16k x 5 cache address comparator
 |
-| three-state
+| 三态逻辑
 | (32)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2163]
@@ 第7,523行： / 第7,526行： @@
 | 16k x 5 cache address comparator
 |
-| three-state
+| 三态逻辑
 | (32)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2164]
@@ 第7,531行： / 第7,534行： @@
 | 16k x 5 cache address comparator with input latches
 |
-| three-state
+| 三态逻辑
 | (32)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74BCT2166]
@@ 第7,563行： / 第7,566行： @@
 | 2个 64-bit FIFO memories (64x1)
 |
-| three-state
+| 三态逻辑
 | (28)
 | [http://www.ti.com/lit/gpn/sn74act2227 SN74ACT2227]
@@ 第7,579行： / 第7,582行： @@
 | 2个 256-bit FIFO memories (256x1)
 |
-| three-state
+| 三态逻辑
 | (28)
 | [http://www.ti.com/lit/gpn/sn74act2227 SN74ACT2229]
@@ 第7,587行： / 第7,590行： @@
 | 512-bit FIFO memory (64x8)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n167 SN74ALS2232A]
@@ 第7,595行： / 第7,598行： @@
 | 576-bit FIFO memory (64x9)
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n175 SN74ALS2233A]
@@ 第7,603行： / 第7,606行： @@
 | 18432-bit bidirectional FIFO memory (2x1024x9)
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n203 SN74ACT2235]
@@ 第7,611行： / 第7,614行： @@
 | 18432-bit bidirectional FIFO memory (2x1024x9)
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n215 SN74ACT2236]
@@ 第7,619行： / 第7,622行： @@
 | 576-bit bidirectional FIFO memory (2x32x9)
 |
-| three-state
+| 三态逻辑
 | 40
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n157 SN74ALS2238]
@@ 第7,627行： / 第7,630行： @@
 | 2个 4-bit bidirectional buffer / line driver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n81 SN74BCT2240]
@@ 第7,635行： / 第7,638行： @@
 | 2个 4-bit bidirectional buffer / line driver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n85 SN74BCT2241]
@@ 第7,643行： / 第7,646行： @@
 | 4-bit bus transceiver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 14
 | [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n951 SN74ALS2242]
@@ 第7,651行： / 第7,654行： @@
 | 4-bit bus transceiver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | (14)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-209724.pdf 74F2243]
@@ 第7,659行： / 第7,662行： @@
 | 2个 4-bit buffer / line driver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n89 SN74BCT2244]
@@ 第7,667行： / 第7,670行： @@
 | 8个 bus transceiver
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n599 SN74ABT2245]
@@ 第7,675行： / 第7,678行： @@
 | 2个 4-line to 1-line multiplexer
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | (16)
 | [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n191 CD74FCT2253]
@@ 第7,683行： / 第7,686行： @@
 | 4个 2-line to 1-line multiplexer
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | (16)
 | [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n197 CD74FCT2257]
@@ 第7,699行： / 第7,702行： @@
 | 8-bit universal shift register
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n363 QS74FCT2299T]
@@ 第7,715行： / 第7,718行： @@
 | 8-bit transparent latch
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | (20)
 | [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n219 CD74FCT2373]
@@ 第7,723行： / 第7,726行： @@
 | 8个 D-type flip-flop with common clock
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | (20)
 | [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n227 CD74FCT2374]
@@ 第7,739行： / 第7,742行： @@
 | 2个 4-bit buffer, inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ic72.com/pdf_file/i/189451.pdf 74THC2400]
@@ 第7,747行： / 第7,750行： @@
 | 11-bit MOS memory driver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 28
 | [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n747 SN74BCT2410]
@@ 第7,755行： / 第7,758行： @@
 | 11-bit MOS memory driver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 28
 | [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n749 SN74BCT2411]
@@ 第7,771行： / 第7,774行： @@
 | 16-bit [[NuBus]] address/data transceiver and register
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n29 SN74BCT2420]
@@ 第7,779行： / 第7,782行： @@
 | 16-bit latched multiplexer/demultiplexer [[NuBus]] transceiver, inverting
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n39 SN74BCT2423]
@@ 第7,787行： / 第7,790行： @@
 | 16-bit latched multiplexer/demultiplexer [[NuBus]] transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n39 SN74BCT2424]
@@ 第7,795行： / 第7,798行： @@
 | [[Macintosh]] Coprocessor Platform [[NuBus]] address/data registered transceiver
 |
-| three-state
+| 三态逻辑
 | (100)
 | [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n49 SN74BCT2425]
@@ 第7,819行： / 第7,822行： @@
 | [[NuBus]] block slave address generator
 |
-| three-state
+| 三态逻辑
 | (20)
 | [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n145 SN74ALS2442]
@@ 第7,827行： / 第7,830行： @@
 | 9-output clock driver with [[Phase-locked loop|PLL]]
 |
-| three-state
+| 三态逻辑
 | (24)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-13/DSA-248016.pdf HD74CDC2509]
@@ 第7,835行： / 第7,838行： @@
 | 10-output clock driver with [[Phase-locked loop|PLL]]
 |
-| three-state
+| 三态逻辑
 | (24)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-13/DSA-248017.pdf HD74CDC2510]
@@ 第7,859行： / 第7,862行： @@
 | 8-bit bus interface latch, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n369 QS74FCT2533T]
@@ 第7,867行： / 第7,870行： @@
 | 8-bit bus interface register, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n375 QS74FCT2534T]
@@ 第7,875行： / 第7,878行： @@
 | 8-bit buffer / line driver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n955 SN74ALS2540]
@@ 第7,883行： / 第7,886行： @@
 | 8-bit buffer / line driver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n955 SN74ALS2541]
@@ 第7,891行： / 第7,894行： @@
 | 8-bit latched transceiver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n399 QS74FCT2543T]
@@ 第7,899行： / 第7,902行： @@
 | 8-bit latched transceiver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n399 QS74FCT2544T]
@@ 第7,907行： / 第7,910行： @@
 | 8-bit transparent latch
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n407 QS74FCT2573T]
@@ 第7,915行： / 第7,918行： @@
 | 8个 D-type flip-flop with common clock
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n413 QS74FCT2574T]
@@ 第7,923行： / 第7,926行： @@
 | 8个 bus transceiver / MOS driver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n763 SN74AS2620]
@@ 第7,931行： / 第7,934行： @@
 | 8个 bus transceiver / MOS driver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n763 SN74AS2623]
@@ 第7,939行： / 第7,942行： @@
 | 8个 bus transceiver / MOS driver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n767 SN74AS2640]
@@ 第7,947行： / 第7,950行： @@
 | 8个 bus transceiver, mix of inverting and non-inverting outputs
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-22/DSA-425742.pdf 74F2643]
@@ 第7,955行： / 第7,958行： @@
 | 8个 bus transceiver / MOS driver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 20
 | [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n767 SN74AS2645]
@@ 第7,963行： / 第7,966行： @@
 | 8个 registered transceiver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n419 QS74FCT2646T]
@@ 第7,971行： / 第7,974行： @@
 | 8个 registered transceiver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n419 QS74FCT2648T]
@@ 第7,979行： / 第7,982行： @@
 | 8个 registered transceiver, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n427 QS74FCT2651T]
@@ 第7,987行： / 第7,990行： @@
 | 8个 registered transceiver, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n427 QS74FCT2652T]
@@ 第7,995行： / 第7,998行： @@
 | 8192-bit PROM (1024x8)
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/n177 SN74S2708]
@@ 第8,003行： / 第8,006行： @@
 | 576-bit FIFO memory (64x9)
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n445 74AC2708]
@@ 第8,027行： / 第8,030行： @@
 | 10-bit D-type flip-flop
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n435 QS74FCT2821T]
@@ 第8,035行： / 第8,038行： @@
 | 9-bit D-type flip-flop with clear
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n435 QS74FCT2823T]
@@ 第8,043行： / 第8,046行： @@
 | 8-bit D-type flip-flop with clear and clock enable
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n435 QS74FCT2825T]
@@ 第8,051行： / 第8,054行： @@
 | 10-bit buffer, non-inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n93 SN74BCT2827A]
@@ 第8,059行： / 第8,062行： @@
 | 10-bit buffer, inverting
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n93 SN74BCT2828A]
@@ 第8,067行： / 第8,070行： @@
 | 8-bit bus transceiver with parity error flip-flop
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n451 QS74FCT2833T]
@@ 第8,075行： / 第8,078行： @@
 | 10-bit transparent latch
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n453 QS74FCT2841T]
@@ 第8,083行： / 第8,086行： @@
 | 9-bit transparent latch with asynchronous reset
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n453 QS74FCT2843T]
@@ 第8,091行： / 第8,094行： @@
 | 8-bit transparent latch with asynchronous reset and multiple output enable
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n453 QS74FCT2845T]
@@ 第8,099行： / 第8,102行： @@
 | 8-bit bus transceiver with parity error latch
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n451 QS74FCT2853T]
@@ 第8,107行： / 第8,110行： @@
 | 10-bit non-inverting bus transceiver
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2861T]
@@ 第8,115行： / 第8,118行： @@
 | 10-bit inverting bus transceiver
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2862T]
@@ 第8,123行： / 第8,126行： @@
 | 9-bit non-inverting bus transceiver with 2个 output enable
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2863T]
@@ 第8,131行： / 第8,134行： @@
 | 9-bit inverting bus transceiver with 2个 output enable
 |
-| three-state, 25&nbsp;Ω series resistor
+| 三态逻辑, 25&nbsp;Ω series resistor
 | 24
 | [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2864T]
@@ 第8,139行： / 第8,142行： @@
 | 8个 bus transceiver and register, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/stream/TexasInstrumentsLVCAndLVDataBook1998/Texas_Instruments_LVC_and_LV_Data_Book_1998#page/n391 SN74LVC2952A]
@@ 第8,147行： / 第8,150行： @@
 | 8个 bus transceiver and register, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n945 74F2953]
@@ 第8,155行： / 第8,158行： @@
 | [[error detection and correction]] (EDAC), equivalent to [[AMD Am2900#Members of the Am2900 family|Am2960]]
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n629 MC74F2960]
@@ 第8,163行： / 第8,166行： @@
 | 4-bit EDAC bus buffer, inverting, equivalent to [[AMD Am2900#Members of the Am2900 family|Am2961]]
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheetspdf.com/pdf-file/501240/Motorola/MC74F2961A/1 MC74F2961A]
@@ 第8,171行： / 第8,174行： @@
 | 4-bit EDAC bus buffer, non-inverting, equivalent to [[AMD Am2900#Members of the Am2900 family|Am2962]]
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheetspdf.com/pdf-file/501240/Motorola/MC74F2961A/1 MC74F2962A]
@@ 第8,262行： / 第8,265行： @@
 | 2个 4-bit buffer / line driver
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n509 IDT74FCT3244]
@@ 第8,278行： / 第8,281行： @@
 | 8个 bidirectional transceiver
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n515 IDT74FCT3245]
@@ 第8,294行： / 第8,297行： @@
 | 8个 bidirectional voltage-translating transceiver
 |
-| three-state
+| 三态逻辑
 | (24)
 | [https://archive.org/details/bitsavers_nationaldaCROSSVOLTLowVoltageLogicSeriesDatabook_18426235/page/n129 74LVX3245]
@@ 第8,326行： / 第8,329行： @@
 | 32-bit latchable transceiver with parity checker / generator
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-22/DSA-420818.pdf 74ACTQ3283]
@@ 第8,334行： / 第8,337行： @@
 | 18-bit synchronous datapath multiplexer
 |
-| three-state
+| 三态逻辑
 | (100)
 | [https://datasheet.datasheetarchive.com/originals/library/Datasheet-019/DSA00332573.pdf 74ABT3284]
@@ 第8,366行： / 第8,369行： @@
 | 8-bit metastable-resistant D-type flip-flop
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00215569.pdf SN74AS3374]
@@ 第8,406行： / 第8,409行： @@
 | 8个 transparent latch
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n521 IDT74FCT3573]
@@ 第8,414行： / 第8,417行： @@
 | 8个 D-type flip flop
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n527 IDT74FCT3574]
@@ 第8,430行： / 第8,433行： @@
 | 2304-bit FIFO memory (64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n361 SN74ABT3611]
@@ 第8,438行： / 第8,441行： @@
 | 4608-bit bidirectional FIFO memory (2x64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n387 SN74ABT3612]
@@ 第8,446行： / 第8,449行： @@
 | 2304-bit FIFO memory (64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n287 SN74ABT3613]
@@ 第8,454行： / 第8,457行： @@
 | 4608-bit bidirectional FIFO memory (2x64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n319 SN74ABT3614]
@@ 第8,462行： / 第8,465行： @@
 | 18432-bit bidirectional FIFO memory (2x256x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n177 SN74ACT3622]
@@ 第8,470行： / 第8,473行： @@
 | 18432-bit FIFO memory (512x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n105 SN74ACT3631]
@@ 第8,478行： / 第8,481行： @@
 | 36864-bit bidirectional FIFO memory (2x512x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n233 SN74ACT3632]
@@ 第8,486行： / 第8,489行： @@
 | 32768-bit bidirectional FIFO memory (2x512x32)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n203 SN74ACT3638]
@@ 第8,494行： / 第8,497行： @@
 | 36864-bit FIFO memory (1024x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n129 SN74ACT3641]
@@ 第8,502行： / 第8,505行： @@
 | 73728-bit bidirectional FIFO memory (2x1024x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n259 SN74ACT3642]
@@ 第8,510行： / 第8,513行： @@
 | 73728-bit FIFO memory (2048x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n153 SN74ACT3651]
@@ 第8,534行： / 第8,537行： @@
 | 10-bit buffer
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n535 IDT74FCT3827]
@@ 第8,558行： / 第8,561行： @@
 | 4个 [[Futurebus]] backplane transceiver
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (20)
 | [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/n313 MC74F3893A]
@@ 第8,566行： / 第8,569行： @@
 | [[P5 (microarchitecture)|Pentium]] clock synthesizer
 |
-| three-state
+| 三态逻辑
 | (28)
 | [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n629 IDT74FCT3907]
@@ 第8,574行： / 第8,577行： @@
 | PLL-based clock driver
 |
-| three-state
+| 三态逻辑
 | (48)
 | [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n619 IDT74FCT3932]
@@ 第8,769行： / 第8,772行： @@
 | 8-bit three-state shift register/latch
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://web.archive.org/web/20170706105747/http://www.ti.com/lit/ds/symlink/cd74hc4094.pdf CD74HC4094]
@@ 第8,793行： / 第8,796行： @@
 | 8-bit 3V/5V translating transceiver
 |
-| three-state
+| 三态逻辑
 | (24)
 | [https://archive.org/details/bitsavers_nationaldaCROSSVOLTLowVoltageLogicSeriesDatabook_18426235/page/n135 74LVX4245]
@@ 第8,801行： / 第8,804行： @@
 | 8-bit latch, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n413 MN74HC4301]
@@ 第8,809行： / 第8,812行： @@
 | 8-bit latch, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n417 MN74HC4302]
@@ 第8,817行： / 第8,820行： @@
 | 8-bit D-type flip-flop, inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n421 MN74HC4303]
@@ 第8,825行： / 第8,828行： @@
 | 8-bit D-type flip-flop, non-inverting outputs
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n425 MN74HC4304]
@@ 第8,833行： / 第8,836行： @@
 | 2个 4-bit buffer, inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n429 MN74HC4305]
@@ 第8,841行： / 第8,844行： @@
 | 2个 4-bit buffer, non-inverting
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n433 MN74HC4306]
@@ 第8,881行： / 第8,884行： @@
 | 8-bit 2个-rank synchronizer
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137795.pdf SN74AS4374]
@@ 第8,889行： / 第8,892行： @@
 | controller for 64k/256k/1M dynamic RAM
 |
-| three-state
+| 三态逻辑
 | 52
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT4503]
@@ 第9,025行： / 第9,028行： @@
 | 8个 bidirectional transceiver
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n417 DM74ALS5245]
@@ 第9,049行： / 第9,052行： @@
 | 11-bit line/memory driver, non-inverting
 |
-| three-state, 25 Ω series resistor
+| 三态逻辑, 25 Ω series resistor
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n605 SN74ABT5400]
@@ 第9,057行： / 第9,060行： @@
 | 11-bit line/memory driver, inverting
 |
-| three-state, 25 Ω series resistor
+| 三态逻辑, 25 Ω series resistor
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n609 SN74ABT5401]
@@ 第9,065行： / 第9,068行： @@
 | 12-bit line/memory driver, non-inverting
 |
-| three-state, 25 Ω series resistor
+| 三态逻辑, 25 Ω series resistor
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n613 SN74ABT5402]
@@ 第9,073行： / 第9,076行： @@
 | 12-bit line/memory driver, inverting
 |
-| three-state, 25 Ω series resistor
+| 三态逻辑, 25 Ω series resistor
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n617 SN74ABT5403]
@@ 第9,089行： / 第9,092行： @@
 | 8个 bidirectional transceiver
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n417 DM74ALS5620]
@@ 第9,172行： / 第9,175行： @@
 | programmable ripple counter with oscillator
 |
-| three-state
+| 三态逻辑
 | (8)
 | [https://assets.nexperia.com/documents/data-sheet/74HC_HCT6323A.pdf 74HC6323A]
@@ 第9,180行： / 第9,183行： @@
 | 64-bit flow-through error detection and correction circuit
 |
-| three-state
+| 三态逻辑
 | (207)
 | [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74AS6364]
@@ 第9,268行： / 第9,271行： @@
 | 576-bit FIFO memory (64x9)
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/highspeedcmosda00sign/page/764 74HC7030]
@@ 第9,284行： / 第9,287行： @@
 | 9-bit bus transceiver with latch
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n641 CD74HC7038]
@@ 第9,340行： / 第9,343行： @@
 | 4个 adjustable comparator with output latches
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 14
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-30/DSA-596949.pdf 74HCT7132]
@@ 第9,412行： / 第9,415行： @@
 | 8个 bus buffer, inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://pdf.datasheet.live/datasheets-1/toshiba/TC74HC7241AP.pdf TC74HC7240AP]
@@ 第9,420行： / 第9,423行： @@
 | 8个 bus buffer, non-inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://pdf.datasheet.live/datasheets-1/toshiba/TC74HC7241AP.pdf TC74HC7241AP]
@@ 第9,428行： / 第9,431行： @@
 | 8个 bus buffer, non-inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [http://pdf.datasheet.live/datasheets-1/toshiba/TC74HC7241AP.pdf TC74HC7244AP]
@@ 第9,436行： / 第9,439行： @@
 | 8个 bus transceiver, non-inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7245]
@@ 第9,476行： / 第9,479行： @@
 | 8-bit bus driver with bidirectional registers
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n625 SN74HC7340]
@@ 第9,484行： / 第9,487行： @@
 | 256-bit FIFO memory (64x4)
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://pdf.datasheetcatalog.com/datasheet/philips/74HC7403.pdf 74HC7403]
@@ 第9,492行： / 第9,495行： @@
 | 320-bit FIFO memory (64x5)
 |
-| three-state
+| 三态逻辑
 | 18
 | [https://pdf1.alldatasheet.com/datasheet-pdf/view/15661/PHILIPS/74HC7404.html 74HC7404]
@@ 第9,500行： / 第9,503行： @@
 | 8个 buffer/line driver, inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://assets.nexperia.com/documents/data-sheet/74HC_HCT7540.pdf 74HC7540]
@@ 第9,508行： / 第9,511行： @@
 | 8个 buffer/line driver, non-inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://assets.nexperia.com/documents/data-sheet/74HC_HCT7541.pdf 74HC7541]
@@ 第9,524行： / 第9,527行： @@
 | 8个 bus transceiver, non-inverting
 |
-| three-state and open-drain
+| 三态逻辑 and open-drain
 | 20
 | [https://archive.org/details/RCA-RCAAdvancedCMOSLogicICs1987OCR/page/n293 CD74AC7623]
@@ 第9,532行： / 第9,535行： @@
 | 8个 bus transceiver, inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7640]
@@ 第9,540行： / 第9,543行： @@
 | 8个 bus transceiver, non-inverting/inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7643]
@@ 第9,548行： / 第9,551行： @@
 | 8个 bus transceiver, non-inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7645]
@@ 第9,564行： / 第9,567行： @@
 | 8-bit noninverting transparent latch with readback
 |
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0048904.pdf MC74HC7793]
@@ 第9,572行： / 第9,575行： @@
 | 18432-bit FIFO memory (1024x18), clocked
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n21 SN74ACT7801]
@@ 第9,580行： / 第9,583行： @@
 | 18432-bit FIFO memory (1024x18)
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n115 SN74ACT7802]
@@ 第9,588行： / 第9,591行： @@
 | 9216-bit FIFO memory (512x18), clocked
 |
-| three-state
+| 三态逻辑
 | (56)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n37 SN74ACT7803]
@@ 第9,596行： / 第9,599行： @@
 | 9216-bit FIFO memory (512x18)
 |
-| three-state
+| 三态逻辑
 | (56)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n127 SN74ACT7804]
@@ 第9,604行： / 第9,607行： @@
 | 4608-bit FIFO memory (256x18), clocked
 |
-| three-state
+| 三态逻辑
 | (56)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n51 SN74ACT7805]
@@ 第9,612行： / 第9,615行： @@
 | 4608-bit FIFO memory (256x18)
 |
-| three-state
+| 三态逻辑
 | (56)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n139 SN74ACT7806]
@@ 第9,620行： / 第9,623行： @@
 | 18432-bit FIFO memory (2048x9), clocked
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n65 SN74ACT7807]
@@ 第9,628行： / 第9,631行： @@
 | 18432-bit FIFO memory (2048x9)
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n151 SN74ACT7808]
@@ 第9,636行： / 第9,639行： @@
 | 18432-bit FIFO memory (1024x18), clocked
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n81 SN74ACT7811]
@@ 第9,644行： / 第9,647行： @@
 | 1152-bit FIFO memory (64x18), clocked
 |
-| three-state
+| 三态逻辑
 | (56)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n99 SN74ACT7813]
@@ 第9,652行： / 第9,655行： @@
 | 1152-bit FIFO memory (64x18)
 |
-| three-state
+| 三态逻辑
 | (56)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n165 SN74ACT7814]
@@ 第9,660行： / 第9,663行： @@
 | 4608-bit bidirectional FIFO memory(2x64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n279 SN74ABT7815]
@@ 第9,668行： / 第9,671行： @@
 | 4608-bit bidirectional FIFO memory(2x64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n291 SN74ABT7816]
@@ 第9,676行： / 第9,679行： @@
 | 2304-bit FIFO memory(64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n293 SN74ABT7817]
@@ 第9,684行： / 第9,687行： @@
 | 2304-bit FIFO memory(64x36)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n295 SN74ABT7818]
@@ 第9,692行： / 第9,695行： @@
 | 18432-bit bidirectional FIFO memory (2x512x18), clocked
 |
-| three-state
+| 三态逻辑
 | (80)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n207 SN74ABT7819]
@@ 第9,700行： / 第9,703行： @@
 | 18432-bit bidirectional FIFO memory (2x512x18)
 |
-| three-state
+| 三态逻辑
 | (80)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n229 SN74ABT7820]
@@ 第9,708行： / 第9,711行： @@
 | 32768-bit bidirectional FIFO memory (2x512x32)
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n317 SN74ACT7821]
@@ 第9,716行： / 第9,719行： @@
 | 32768-bit bidirectional FIFO memory (2x512x32), clocked
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n325 SN74ACT7822]
@@ 第9,724行： / 第9,727行： @@
 | 36864-bit FIFO memory (1024x36), clocked
 |
-| three-state
+| 三态逻辑
 | (120)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n333 SN74ACT7823]
@@ 第9,732行： / 第9,735行： @@
 | 18432-bit FIFO memory (1024x18), clocked
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n479 SN74ACT7881]
@@ 第9,740行： / 第9,743行： @@
 | 36864-bit FIFO memory (2048x18), clocked
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n495 SN74ACT7882]
@@ 第9,748行： / 第9,751行： @@
 | 73728-bit FIFO memory (4096x18), clocked
 |
-| three-state
+| 三态逻辑
 | (68)
 | [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n511 SN74ACT7884]
@@ 第9,764行： / 第9,767行： @@
 | 10-bit inverting/non-inverting buffer
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 24
 | [http://www.ti.com/lit/gpn/sn74lv8151 SN74LV8151]
@@ 第9,772行： / 第9,775行： @@
 | 8-bit serial-to-parallel interface
 |
-| three-state or open-collector
+| 三态逻辑 or open-collector
 | 20
 | [http://www.ti.com/lit/gpn/sn74lv8153 SN74LV8153]
@@ 第9,780行： / 第9,783行： @@
 | 2个 16-bit counters with output registers
 |
-| three-state
+| 三态逻辑
 | 20
 | [http://www.ti.com/lit/gpn/sn74lv8154 SN74LV8154]
@@ 第9,796行： / 第9,799行： @@
 | 8个 inverting buffer with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n23 SN74BCT8240A]
@@ 第9,804行： / 第9,807行： @@
 | 8个 non-inverting buffer with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n43 SN74BCT8244A]
@@ 第9,812行： / 第9,815行： @@
 | 8个 bus transceiver with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n735 SN74ABT8245]
@@ 第9,820行： / 第9,823行： @@
 | 8个 D-type latch with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n85 SN74BCT8373A]
@@ 第9,828行： / 第9,831行： @@
 | 8个 D-type edge-triggered flip-flop with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n105 SN74BCT8374A]
@@ 第9,836行： / 第9,839行： @@
 | expandable error checker / corrector
 |
-| three-state
+| 三态逻辑
 | 48
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n541 SN74ALS8400]
@@ 第9,844行： / 第9,847行： @@
 | 8-bit buffer, selectable inverting/non-inverting
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | 20
 | [https://datasheet.datasheetarchive.com/originals/distributors/DKDS41/DSANUWW0029467.pdf SN74AHC8541]
@@ 第9,852行： / 第9,855行： @@
 | 8个 registered bus transceiver with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n757 SN74ABT8543]
@@ 第9,860行： / 第9,863行： @@
 | 8个 bus transceiver and register with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n765 SN74ABT8646]
@@ 第9,868行： / 第9,871行： @@
 | 8个 bus transceiver and register with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n775 SN74ABT8652]
@@ 第9,876行： / 第9,879行： @@
 | 16-bit microprogram sequencer, cascadable
 |
-| three-state
+| 三态逻辑
 | (84)
 | [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n19 SN74ACT8818]
@@ 第9,884行： / 第9,887行： @@
 | 32-bit registered ALU
 |
-| three-state
+| 三态逻辑
 | (208)
 | [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n79 SN74ACT8832]
@@ 第9,892行： / 第9,895行： @@
 | 40-bit register file
 |
-| three-state
+| 三态逻辑
 | (156)
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n545 SN74AS8834]
@@ 第9,900行： / 第9,903行： @@
 | 16-bit microprogram sequencer, cascadable
 |
-| three-state
+| 三态逻辑
 | (156)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0053260.pdf SN74AS8835]
@@ 第9,908行： / 第9,911行： @@
 | 32x32-bit multiplier/accumulator
 |
-| three-state
+| 三态逻辑
 | (156)
 | [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n273 SN74ACT8836]
@@ 第9,916行： / 第9,919行： @@
 | 64-bit floating point unit
 |
-| three-state
+| 三态逻辑
 | (208)
 | [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n307 SN74ACT8837]
@@ 第9,924行： / 第9,927行： @@
 | 64-bit barrel shifter
 |
-| three-state
+| 三态逻辑
 | (84)
 | [https://archive.org/details/bitsavers_tidataBook_28346484/page/n555 SN74AS8838]
@@ 第9,932行： / 第9,935行： @@
 | 32-bit shuffle/exchange network
 |
-| three-state
+| 三态逻辑
 | (85)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0053259.pdf SN74AS8839]
@@ 第9,940行： / 第9,943行： @@
 | digital crossbar switch
 |
-| three-state
+| 三态逻辑
 | (156)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-110/DSAP0010220.pdf SN74AS8840]
@@ 第9,948行： / 第9,951行： @@
 | digital crossbar switch
 |
-| three-state
+| 三态逻辑
 | (156)
 | [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n435 SN74ACT8841]
@@ 第9,956行： / 第9,959行： @@
 | 64-bit floating point and integer unit
 |
-| three-state
+| 三态逻辑
 | (208)
 | [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n461 SN74ACT8847]
@@ 第9,964行： / 第9,967行： @@
 | 32-bit vector processor unit
 |
-| three-state
+| 三态逻辑
 | (208)
 | [https://archive.org/details/TexasInstruments-TI-Data-SN74ACT8800Family32-BitCMOSProcessorBuildingBlocks1990OCR/page/n495 SN74ACT8867]
@@ 第9,972行： / 第9,975行： @@
 | 8个 registered bus transceiver with [[JTAG]] port
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n785 SN74ABT8952]
@@ 第9,980行： / 第9,983行： @@
 | 8-bit bidirectional latched [[FutureBus]] transceiver, inverting
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 28
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8960_PhilipsSemiconductors.pdf 74F8960]
@@ 第9,988行： / 第9,991行： @@
 | 8-bit bidirectional latched [[FutureBus]] transceiver, non-inverting
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | 28
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8960_PhilipsSemiconductors.pdf 74F8961]
@@ 第9,996行： / 第9,999行： @@
 | 9-bit bidirectional latched [[FutureBus]] transceiver, inverting
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (44)
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8962_PhilipsSemiconductors.pdf 74F8962]
@@ 第10,004行： / 第10,007行： @@
 | 9-bit bidirectional latched [[FutureBus]] transceiver, non-inverting
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (44)
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8962_PhilipsSemiconductors.pdf 74F8963]
@@ 第10,012行： / 第10,015行： @@
 | 9-bit bidirectional latched [[FutureBus]] transceiver, latch select
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (44)
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8965_PhilipsSemiconductors.pdf 74F8965]
@@ 第10,020行： / 第10,023行： @@
 | 9-bit bidirectional latched [[FutureBus]] transceiver, idle arbitration request / output
 |
-| three-state and open-collector
+| 三态逻辑 and open-collector
 | (44)
 | [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8965_PhilipsSemiconductors.pdf 74F8966]
@@ 第10,028行： / 第10,031行： @@
 | [[JTAG]] test access port master with 8-bit host interface
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n795 SN74LVT8980]
@@ 第10,036行： / 第10,039行： @@
 | linkable, multidrop-addressable [[JTAG]] transceiver
 |
-| three-state
+| 三态逻辑
 | (64)
 | [http://www.ti.com/lit/gpn/sn74lvt8986 SN74LVT8986]
@@ 第10,044行： / 第10,047行： @@
 | [[JTAG]] test access port master with 16-bit host interface
 |
-| three-state
+| 三态逻辑
 | (44)
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n825 SN74ACT8990]
@@ 第10,068行： / 第10,071行： @@
 | scan-controlled [[JTAG]] concatenator
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n887 SN74ACT8997]
@@ 第10,076行： / 第10,079行： @@
 | scan-controlled [[JTAG]] multiplexer
 |
-| three-state
+| 三态逻辑
 | 28
 | [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n911 SN74ACT8999]
@@ 第10,164行： / 第10,167行： @@
 | 8-bit shift register (serial in/out, parallel in/out)
 | Schmitt trigger
-| three-state
+| 三态逻辑
 | (16)
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-SFU3/DSASFU100040800.pdf TC74VHC9164]
@@ 第10,172行： / 第10,175行： @@
 | 9-bit buffer / line driver, inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-211521.pdf 74FR9240]
@@ 第10,180行： / 第10,183行： @@
 | 9-bit buffer / line driver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-212907.pdf 74FR9244]
@@ 第10,188行： / 第10,191行： @@
 | 9-bit bidirectional transceiver, non-inverting
 |
-| three-state
+| 三态逻辑
 | 24
 | [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-203499.pdf 74FR9245]
@@ 第10,196行： / 第10,199行： @@
 | programmable ripple counter with oscillator
 |
-| three-state
+| 三态逻辑
 | (8)
 | [http://pdf.datasheetcatalog.com/datasheet/philips/74HCT7731.pdf 74HC9323A]
@@ 第10,204行： / 第10,207行： @@
 | 16×16-bit multiplier/accumulator (compatible to [[List of AMD Am2900 and Am29000 families#Am29500 Family|Am29510]] and [[Digital signal processor#Background|TDC1010]])
 |
-| three-state
+| 三态逻辑
 | (68)
 | 74HC9510<ref name=hcmostb/>{{rp|534}}
@@ 第10,236行： / 第10,239行： @@
 | 4-bit bidirectional universal shift register
 |
-| three-state
+| 三态逻辑
 | 16
 | [https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n613 CD74HC40104]
@@ 第10,244行： / 第10,247行： @@
 | 64-bit FIFO memory (16x4)
 |
-| three-state
+| 三态逻辑
 | 16
 | [http://www.ti.com/lit/gpn/cd74hc40105 CD74HC40105]
@@ 第10,267行： / 第10,270行： @@
 |-
 | 74x1G00
-| 1个 2输入 [[NAND gate]]
+| 1个 2输入 [[与非门]]
 |
 |
@@ 第10,346行： / 第10,349行： @@
 | 1个 1-of-2 non-inverting [[multiplexer]], deselected output is 3-state
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 6
 | [https://assets.nexperia.com/documents/data-sheet/74LVC1G18.pdf LVC]
@@ 第10,458行： / 第10,461行： @@
 | 1个 configurable 15-function gate, active-low enable
 | schmitt trigger
-| three-state
+| 三态逻辑
 | 8
 | [https://assets.nexperia.com/documents/data-sheet/74LVC1G99.pdf LVC]
@@ 第10,472行： / 第10,475行： @@
 | 1个 buffer gate, active-low enable
 |
-| three-state
+| 三态逻辑
 | 5
 | [https://assets.nexperia.com/documents/data-sheet/74LVC1G125.pdf LVC]
@@ 第10,479行： / 第10,482行： @@
 | 1个 buffer gate, active-high enable
 |
-| three-state
+| 三态逻辑
 | 5
 | [https://assets.nexperia.com/documents/data-sheet/74LVC1G126.pdf LVC]
@@ 第10,521行： / 第10,524行： @@
 | 1个 非门, active-low enable
 |
-| three-state
+| 三态逻辑
 | 5
 | [https://assets.nexperia.com/documents/data-sheet/74LVC1G240.pdf LVC]
@@ 第10,535行： / 第10,538行： @@
 | 1个 D-type transparent latch, negative-edge latching, Q output, active-low enable
 |
-| three-state
+| 三态逻辑
 | 6
 | [http://www.ti.com/lit/gpn/sn74lvc1g373 LVC]
@@ 第10,542行： / 第10,545行： @@
 | 1个 D-type flip-flop, positive-edge trigger, Q output, active-low enable
 |
-| three-state
+| 三态逻辑
 | 6
 | [http://www.ti.com/lit/gpn/sn74lvc1g374 LVC]
@@ 第10,717行： / 第10,720行： @@
 | 2个 buffer, active-low enable
 |
-| [[Three-state logic|three-state]]
+| [[三态逻辑|三态逻辑]]
 | 8
 | [https://assets.nexperia.com/documents/data-sheet/74LVC2G125.pdf LVC]
@@ 第10,724行： / 第10,727行： @@
 | 2个 buffer, active-high enable
 |
-| three-state
+| 三态逻辑
 | 8
 | [https://assets.nexperia.com/documents/data-sheet/74LVC2G126.pdf LVC]
@@ 第10,738行： / 第10,741行： @@
 | 2个 非门, active-low enable
 |
-| three-state
+| 三态逻辑
 | 8
 | [https://assets.nexperia.com/documents/data-sheet/74LVC2G240.pdf LVC]
@@ 第10,745行： / 第10,748行： @@
 | 2个 buffer, active-low and active-high enables
 |
-| three-state
+| 三态逻辑
 | 8
 | [https://assets.nexperia.com/documents/data-sheet/74LVC2G241.pdf LVC]