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[[百问网imx6ull开发板]]
{{Use dmy dates|date=January 2020|cs1-dates=y}}
The following is a '''list of 7400-series digital logic integrated circuits'''.  In the mid-1960s, the original [[7400-series integrated circuits|7400-series]] [[integrated circuit]]s were introduced by [[Texas Instruments]] with the prefix "SN" to create the name SN74xx. Due to the popularity of these parts, other manufacturers released pin-to-pin compatible [[logic gate|logic]] devices and kept the 7400 sequence number as an aid to identification of compatible parts.  However, other manufacturers use different prefixes and suffixes on their part numbers.
 
==概述==
 
一些TTL逻辑器件具有扩展的军事规格温度范围。这些部件在部件号中以 '''54''' 而不是 '''74''' 为前缀.<ref>{{cite web |title=1967–1968 Integrated Circuits Catalog (page 10) |url=https://archive.org/details/bitsavers_tidataBookts196768_16942634/page/n10 |publisher= [[Texas Instruments]] |access-date=January 14, 2020}}</ref>
 
德州仪器（TI）部件上短暂的'''64'''前缀表示工业温度范围;到1973年，这个前缀已经从TI文献中删除了。最新的7400系列部件采用[[CMOSS]]或[[BiCMOSS]]技术,而不是TTL制造。具有单个门电路的表面贴装器件（通常采用5或6引脚封装）以'''741G'''而不是'''74'''为前缀。
 
Some manufacturers released some [[4000-series integrated circuits|4000-series]] equivalent CMOS circuits with a 74 prefix, for example, the 74HC4066<ref>{{cite web |title=RCA Solid State Databook High Speed CMOS Logic (1988, page 536) |url=https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n536 |publisher= [[RCA]] |access-date=January 14, 2020}}</ref> was a replacement for the 4066 with slightly different electrical characteristics (different power-supply voltage ratings, higher frequency capabilities, lower "on" resistances in analog switches, etc.). See [[List of 4000-series integrated circuits]].
Conversely, the 4000-series has "borrowed" from the 7400 series{{snd}} such as the CD40193 and CD40161 being pin-for-pin ''functional'' replacements for 74C193 and 74C161.
 
Older TTL parts made by manufacturers such as [[Signetics]], [[Motorola]], [[Mullard]] and [[Siemens]] may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8输入 [[与非门]] like a 7430.
 
A few alphabetic characters to designate a specific [[7400-series integrated circuits#Families|logic subfamily]] may immediately follow the '''74''' or '''54''' in the part number, e.g., 74LS74 for low-power [[Schottky diode|Schottky]]. Some CMOS parts such as 74HCT74 for high-speed [[CMOS]] with TTL-compatible input thresholds are functionally similar to the TTL part. Not all functions are available in all families.
The generic descriptive feature of these alphabetic characters was diluted by various companies participating in the market at its peak and are not always consistent especially with more recent offerings. The National Semiconductor trademarks of the words FAST<ref>{{cite web |title=FAST Advanced Schottky TTL Logic (1988, cover page) |url=https://archive.org/details/bitsavers_nationaldaFASTDatabook_31226275 |publisher= [[National Semiconductor]] |access-date=January 14, 2020}}</ref> and FACT
<ref>{{cite web |title=FACT Advanced CMOS Logic Databook (1990, cover page)) |url=https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242 |publisher= [[National Semiconductor]] |access-date=January 14, 2020}}</ref> are usually cited in the descriptions from other companies when describing their own unique designations.<ref>{{cite web |title=Samsung High Performance CMOS Data Book 1988 (page 31) |url=https://archive.org/details/bitsavers_samsungdatghPerformanceCMOSLogicDataBook_50512171/page/n31 |publisher= [[Samsung]] |access-date=January 14, 2020}}</ref><ref>{{cite web |title=1990/1991 Logic Databook (page 401) |url=https://archive.org/details/bitsavers_idtdataBooook_39008706/page/n401 |publisher=[[Integrated Device Technology]] |access-date=January 14, 2020}}</ref>
 
In a few instances, such as the 7478 and 74107, the same suffix in different families do not have completely equivalent logic functions.
 
Another extension to the series is the '''7416xxx''' variant, representing mostly the 16-bit-wide counterpart of otherwise 8-bit-wide "base" chips with the same three ending digits. Thus e.g. a "7416373" would be the 16-bit-wide equivalent of a "74373". Some 7416xxx parts, however, do not have a direct counterpart from the standard 74xxx range but deliver new functionality instead, which needs making use of the 7416xxx series' higher pin count. For more details, refer primarily to the Texas Instruments documentation mentioned in the [[#References|References]] section.
 
For CMOS (AC, HC, etc.) subfamilies, read "open drain" for "[[open collector]]" in the table below.
 
There are a few numeric suffixes that have multiple conflicting assignments, such as the 74453.
 
==逻辑门==
[[File:Logique74ls51.svg|thumb|right|Schematic of 74LS51 IC consists of a 3-3 AOI gate and 2-2 AOI gate. AOI means [[AND-OR-Invert]] (AND-NOR). Most AOI chips are currently obsolete.]]
{{See also|Logic gate|Logic level|Logic family}}
由于有许多种7400 系列芯片，为了更轻松地选择需要的芯片，以下对芯片类型进行分组（仅包括组合逻辑门）。
 
对于本节中的芯片编号，“x”表示  [[7400-series integrated circuits#Families|7400-series logic family]]，例如 LS、ALS、HCT、AHCT、HC、AHC、LVC 等。
 
;Normal inputs / push–pull outputs
:{| class="wikitable"
|-
! 种类 !! 缓冲器 !! 非门
|-
| 6个 1输入 || 74x34 || 74x04
|}
:{| class="wikitable"
|-
! 种类 !! AND与门 !! NAND与非门 !! OR或门 !! NOR或非门 !! XOR异或门 !! XNOR异或非门
|-
| 4个 2输入 || 74x08 || 74x00 || 74x32 || 74x02 || 74x86 || 74x7266
|-
| 3个 3输入 || 74x11 || 74x10 || 74x4075 || 74x27 || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a
|-
| 2个 4输入 || 74x21 || 74x20 || 74x4072 || 74x29 || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a
|-
| 1个 8输入 || style="background: grey; text-align: center;" | n/a || 74x30 || 74x4078 || 74x4078 || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a
|}
 
;Schmitt-trigger inputs / push–pull outputs
:{| class="wikitable"
|-
! 种类 !! 缓冲器 !! 非门
|-
| 6个 1输入 || 74x7014 || 74x14
|}
:{| class="wikitable"
|-
! 种类 !! AND与门 !! NAND与非门 !! OR或门 !! NOR或非门
|-
| 4个 2输入 || 74x7001 || 74x132 || 74x7032 || 74x7002
|-
| 2个 4输入 || style="background: grey; text-align: center;" | n/a || 74x13 || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a
|}
 
;Normal inputs / open-collector outputs
:{| class="wikitable"
|-
! 种类 !! 缓冲器 !! 非门
|-
| 6个 1输入 || 74x07 || 74x05
|}
:{| class="wikitable"
|-
! 种类 !! AND与门 !! NAND与非门 !! OR或门 !! NOR或非门 !! XOR异或门 !! XNOR异或非门
|-
| 4个 2输入 || 74x09 || 74x03 || style="background: grey; text-align: center;" | n/a || 74x33 || 74x136 || 74x266
|-
| 3个 3输入 || 74x15 || 74x12 || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a
|-
| 2个 4输入 || style="background: grey; text-align: center;" | n/a || 74x22 || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a || style="background: grey; text-align: center;" | n/a
|}
 
;Schmitt-trigger inputs / three-state outputs
:{| class="wikitable"
|-
! 种类 !! 缓冲器
!非门
|-
| 8个 1输入 || 74x241
74x244
| 74x240
|}
 
;AND-OR-invert (AOI) logic gates
: NOTE: in past decades, a number of [[AND-OR-invert]] (AOI) parts were available in 7400 TTL families, but currently most are obsolete.
* SN5450 = 2个 2-2 AOI gate, one is expandable (SN54 is military version of SN74)
* SN74LS51 = 2-2 AOI gate and 3-3 AOI gate
* SN54LS54 = single 2-3-3-2 AOI gate
 
==较多pin脚的芯片==
 
本节中的器件的引脚数为14个及以上。较小芯片编号是在20世纪60年代和70年代发布的，然后几十年来逐步有更高的芯片编号。IC制造商继续制造那些广泛使用的芯片，而其他许多芯片编号被认为是过时的，并不再生产了。较旧的芯片型号可能从有限的卖家处获得，比如 [[new old stock]](NOS)即新的原始库存，尽管有些芯片型号更难找到。
 
 
对于下表：
* 芯片型号列{{snd}} "x"是 [[7400-series integrated circuits#Families|logic subfamily]] 的占位符. 例如，74x00芯片在“LS”逻辑系列中就是“74LS00”。
* 描述列{{snd}} 包括术语施密特触发器、集电极开路/漏极开路、三态被移动到输入列和输出列，以便更容易地按这些特征进行排序。
* 输入列{{snd}} 空白单元格表示正常输入。
* 输出列{{snd}} 空白单元格表示"totem pole" 输出，也称为 [[push–pull output]]，能够驱动同一逻辑子类芯片的十个标准输入 ([[fan-out]] N<sub>O</sub>&nbsp;=&nbsp;10). 具有更高输出电流的芯片型号通常称为驱动器或缓冲器。
* Pin数目列{{snd}} [[雙列直插封裝]] (DIP) 封装的pin脚数目; 括号（圆括号）中的数字表示该 IC 没有已知的双列直插式封装版本。
 
 
{|class="wikitable sortable"
! {{TOC tab|Part number|74x00 – 74x99}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|7400}}
| 74x00
| 4
| 4个 2输入 [[与非门|NAND与非门]]
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls00 SN74LS00]<!--July2018-->
|- {{anchor|7401}}
| 74x01
| 4
| 4个 2输入 NAND与非门
|
| [[Open collector|open-collector]]
| 14
| [http://www.ti.com/lit/gpn/sn5401 SN74LS01]<!--July2018-->
|- {{anchor|7402}}
| 74x02
| 4
| 4个 2输入 [[NOR 或非门]]
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls02 SN74LS02]<!--July2018-->
|- {{anchor|7403}}
| 74x03
| 4
| 4个 2输入 NAND与非门
|
| open-collector
| 14
| [http://www.ti.com/lit/gpn/sn54ls03 SN74LS03]<!--May '21 July2018-->
|- {{anchor|7404}}
| 74x04
| 6
| 6个 [[非门]]
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls04 SN74LS04]<!--July2018-->
|- {{anchor|7405}}
| 74x05
| 6
| 6个 非门
|
| open-collector
| 14
| [http://www.ti.com/lit/gpn/sn74ls05 SN74LS05]<!--July2018-->
|- {{anchor|7406}}
| 74x06
| 6
| 6个 非门
|
| open-collector 30&nbsp;V / 40&nbsp;mA
| 14
| [http://www.ti.com/lit/gpn/sn74ls06 SN74LS06]<!--July2018-->
|- {{anchor|7407}}
| 74x07
| 6
| 6个 [[buffer gate]]
|
| open-collector 30&nbsp;V / 40&nbsp;mA
| 14
| [http://www.ti.com/lit/gpn/sn74ls07 SN74LS07]<!--July2018-->
|- {{anchor|7408}}
| 74x08
| 4
| 4个 2输入 [[AND gate]]
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls08 SN74LS08]<!--July2018-->
|- {{anchor|7409}}
| 74x09
| 4
| 4个 2输入 AND与门
|
| open-collector
| 14
| [http://www.ti.com/lit/gpn/sn74ls09 SN74LS09]<!--July2018-->
|- {{anchor|7410}}
| 74x10
| 3
| 3个 3输入 NAND与非门
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls10 SN74LS10]<!--July2018-->
|- {{anchor|7411}}
| 74x11
| 3
| 3个 3输入 AND与门
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls11 SN74LS11]<!--July2018-->
|- {{anchor|7412}}
| 74x12
| 3
| 3个 3输入 NAND与非门
|
| open-collector
| 14
| [http://pdf.datasheetcatalog.com/datasheet/motorola/SN54LS12J.pdf SN74LS12]<!--July2018-->
|- {{anchor|7413}}
| 74x13
| 2
| 2个 4输入 NAND与非门
| [[Schmitt trigger]]
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n125 SN74LS13]<!--December2019-->
|- {{anchor|7414}}
| 74x14
| 6
| 6个 非门
| Schmitt trigger
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls14 SN74LS14]<!--July2018-->
|- {{anchor|7415}}
| 74x15
| 3
| 3个 3输入 AND与门
|
| open-collector
| 14
| [http://pdf.datasheetcatalog.com/datasheet/motorola/74LS15.pdf SN74LS15]<!--July2018-->
|- {{anchor|7416}}
| 74x16
| 6
| 6个 非门
|
| open-collector 15&nbsp;V / 40&nbsp;mA
| 14
| [http://www.ti.com/lit/gpn/sn7416 SN7416]<!--July2018-->
|- {{anchor|7417}}
| 74x17
| 6
| 6个 buffer gate
|
| open-collector 15&nbsp;V / 40&nbsp;mA
| 14
| [http://www.ti.com/lit/gpn/sn7417 SN7417]<!--July2018-->
|- {{anchor|7418}}
| 74x18
| 2
| 2个 4输入 NAND与非门
| Schmitt trigger
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n149 SN74LS18]<!--July2018-->
|- {{anchor|7419}}
| 74x19
| 6
| 6个 非门
| Schmitt trigger
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n149 SN74LS19]<!--July2018-->
|- {{anchor|7420}}
| 74x20
| 2
| 2个 4输入 NAND与非门
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls20 SN74LS20]<!--July2018-->
|- {{anchor|7421}}
| 74x21
| 2
| 2个 4输入 AND与门
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls21 SN74LS21]<!--July2018-->
|- {{anchor|7422}}
| 74x22
| 2
| 2个 4输入 NAND与非门
|
| open-collector
| 14
| [http://pdf.datasheetcatalog.com/datasheets/270/331402_DS.pdf SN74LS22]<!--July2018-->
|- {{anchor|7423}}
| 74x23
| 2
| 2个 4输入 NOR 或非门 with strobe, one gate expandable with 74x60
|
|
| 16
| [http://www.ti.com/lit/gpn/sn5423 SN7423]<!--July2018-->
|- {{anchor|7424}}
| 74x24
| 4
| 4个 2输入 NAND与非门
| Schmitt trigger
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n149 SN74LS24]<!--July2018-->
|- {{anchor|7425}}
| 74x25
| 2
| 2个 4输入 NOR 或非门 with strobe
|
|
| 14
| [http://www.ti.com/lit/gpn/sn7425 SN7425]<!--July2018-->
|- {{anchor|7426}}
| 74x26
| 4
| 4个 2输入 NAND与非门
|
| open-collector 15&nbsp;V
| 14
| [http://www.ti.com/lit/gpn/sn74ls26 SN74LS26]<!--July2018-->
|- {{anchor|7427}}
| 74x27
| 3
| 3个 3输入 NOR 或非门
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls27 SN74LS27]<!--July2018-->
|- {{anchor|7428}}
| 74x28
| 4
| 4个 2输入 NOR 或非门
|
| driver N<sub>O</sub>=30
| 14
| [http://www.ti.com/lit/gpn/sn5428 SN74LS28]<!--July2018-->
|- {{anchor|7429}}
| 74x29
| 2
| 2个 4输入 NOR 或非门
|
|
| 14
| [https://archive.org/stream/bitsavers_derivationates1974DigitalIntegratedCircuitDataBook_79049866#page/n101 US7429A]
|- {{anchor|7430}}
| 74x30
| 1
| 1个 8输入 NAND与非门
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls30 SN74LS30]<!--July2018-->
|- {{anchor|7431}}
| 74x31
| 6
| 6个 delay elements (two 6ns, two 23-32ns, two 45-48ns)
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls31 SN74LS31]<!--July2018-->
|- {{anchor|7432}}
| 74x32
| 4
| 4个 2输入 [[OR gate]]
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls32 SN74LS32]<!--July2018-->
|- {{anchor|7433}}
| 74x33
| 4
| 4个 2输入 NOR 或非门
|
| open-collector driver N<sub>O</sub>=30
| 14
| [http://www.ti.com/lit/gpn/sn74ls33 SN74LS33]<!--July2018-->
|- {{anchor|7434}}
| 74x34
| 6
| 6个 buffer gate
|
|
| 14
| [http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009389.PDF MM74HC34]<!--July2018-->
|- {{anchor|7435}}
| 74x35
| 6
| 6个 buffer gate
|
| open-collector
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n101 SN74ALS35]
|- {{anchor|7436}}
| 74x36
| 4
| 4个 2输入 NOR 或非门 (different pinout than 7402)
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n81 SN74HC36]
|- {{anchor|7437}}
| 74x37
| 4
| 4个 2输入 NAND与非门
|
| driver N<sub>O</sub>=30
| 14
| [http://www.ti.com/lit/gpn/sn74ls37 SN74LS37]<!--July2018-->
|- {{anchor|7438}}
| 74x38
| 4
| 4个 2输入 NAND与非门
|
| open-collector driver N<sub>O</sub>=30
| 14
| [http://www.ti.com/lit/gpn/sn74ls38 SN74LS38]<!--July2018-->
|- {{anchor|7439}}
| 74x39
| 4
| 4个 2输入 NAND与非门 (different [[pinout]] than 7438)
|
| open-collector 60&nbsp;mA
| 14
| [http://pdf.datasheetcatalog.com/datasheets/90/338005_DS.pdf SN7439]<!--July2018-->
|- {{anchor|7440}}
| 74x40
| 2
| 2个 4输入 NAND与非门
|
| driver N<sub>O</sub>=30
| 14
| [http://pdf.datasheetcatalog.com/datasheet/motorola/SN54LS40J.pdf SN74LS40]<!--July2018-->
|- {{anchor|7441}}
| 74x41
| 1
| [[binary-coded decimal|BCD]] to decimal [[Binary decoder|decoder]] / [[Nixie tube]] driver
|
| open-collector 70&nbsp;V
| 16
| [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n146 DM7441A]<!--July2018-->
|- {{anchor|7442}}
| 74x42
| 1
| BCD to decimal decoder
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls42 SN74LS42]<!--July2018-->
|- {{anchor|7443}}
| 74x43
| 1
| [[excess-3]] to decimal decoder
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n231 SN7443A]<!--July2018-->
|- {{anchor|7444}}
| 74x44
| 1
| [[Gray code]] to decimal decoder
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n231 SN7444A]<!--July2018-->
|- {{anchor|7445}}
| 74x45
| 1
| BCD to decimal decoder/driver
|
| open-collector 30&nbsp;V / 80&nbsp;mA
| 16
| [http://www.ti.com/lit/gpn/sn7445 SN7445]<!--July2018-->
|- {{anchor|7446}}
| 74x46
| 1
| BCD to [[seven-segment display|7-segment display]] decoder/driver
|
| open-collector 30&nbsp;V
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n244 SN7446A]<!--January 2020-->
|- {{anchor|7447}}
| 74x47
| 1
| BCD to 7-segment decoder/driver
|
| open-collector 15&nbsp;V
| 16
| [http://www.ti.com/lit/gpn/sn74ls47 SN74LS47]<!--July2018-->
|- {{anchor|7448}}
| 74x48
| 1
| BCD to 7-segment decoder/driver
|
| open-collector, 2&nbsp;kΩ [[Pull-up resistor|pull-up]]
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n244 SN74LS48]<!--January 2020-->
|- {{anchor|7449}}
| 74x49
| 1
| BCD to 7-segment decoder/driver
|
| open-collector
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n244 SN74LS49]<!--January 2020-->
|- {{anchor|7450}}
| 74x50
| 2
| 2个 2-2输入 [[AND-OR-Invert]] gate, one gate expandable
|
|
| 14
| [http://www.ti.com/lit/gpn/sn5450 SN7450]<!--July2018-->
|- {{anchor|7451}}
| 7451, 74H51, 74S51
| 2
| 2个 2-2输入 AND-OR-Invert (AOI) gate
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls51 SN7451]<!--July2018-->
|-
| 74L51, 74LS51
| 2
| 3-3输入 [[AND-OR-Invert]] gate and 2-2输入 AND-OR-Invert gate
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls51 SN74LS51]<!--July2018-->
|- {{anchor|7452}}
| 74x52
| 1
| 3-2-2-2输入 AND-OR gate, expandable with 74x61
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n271 SN74H52]<!--July2018-->
|- {{anchor|7453}}
| 7453
| 1
| 2-2-2-2输入 AND-OR-Invert gate, expandable
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n273 SN7453]<!--July2018-->
|-
| 74H53
| 1
| 3-2-2-2输入 AND-OR-Invert gate, expandable
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n273 SN74H53]<!--July2018-->
|- {{anchor|7454}}
| 7454
| 1
| 2-2-2-2输入 AND-OR-Invert gate
|
|
| 14
| [http://www.ti.com/lit/gpn/sn5454 SN7454]<!--July2018-->
|-
| 74H54
| 1
| 3-2-2-2输入 AND-OR-Invert gate
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n279 SN74H54]
|-
| 74L54, 74LS54
| 1
| 3-3-2-2输入 AND-OR-Invert gate
|
|
| 14
| [http://www.ti.com/lit/gpn/sn5454 SN74LS54]<!--July2018-->
|- {{anchor|7455}}
| 74x55
| 1
| 4-4输入 AND-OR-Invert gate, 74H55 is expandable
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n287 SN74LS55]<!--July2018-->
|- {{anchor|7456}}
| 74x56
| 1
| 50:1 [[frequency divider]]
|
|
| 8
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n291 SN74LS56]<!--July2018-->
|- {{anchor|7457}}
| 74x57
| 1
| 60:1 frequency divider
|
|
| 8
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n291 SN74LS57]<!--July2018-->
|- {{anchor|7458}}
| 74x58
| 2
| 3-3输入 AND-OR gate and 2-2输入 AND-OR gate
|
|
| 14
| [https://media.digikey.com/pdf/Data%20Sheets/NXP%20PDFs/74HC58.pdf 74HC58]<!--July2018-->
|- {{anchor|7459}}
| 74x59
| 2
| 2个 3-2输入 AND-OR-Invert gate
|
|
| 14
| [https://archive.org/stream/bitsavers_derivationates1974DigitalIntegratedCircuitDataBook_79049866#page/n103 US7459A]
|- {{anchor|7460}}
| 74x60
| 2
| 2个 4输入 expander for 74x23, 74x50, 74x53, 74x55
|
| {{Unknown|{{sp}}}}
| 14
| [http://pdf.datasheetcatalog.com/datasheets/166/501736_DS.pdf SN7460]<!--July2018-->
|- {{anchor|7461}}
| 74x61
| 3
| 3个 3输入 expander for 74x52
|
| {{Unknown|{{sp}}}}
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n299 SN74H61]<!--July2018-->
|- {{anchor|7462}}
| 74x62
| 1
| 3-3-2-2输入 AND-OR expander for 74x50, 74x53, 74x55
|
| {{Unknown|{{sp}}}}
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n301 SN74H62]<!--July2018-->
|- {{anchor|7463}}
| 74x63
| 6
| 6个 current sensing interface gates
| {{Unknown|{{sp}}}}
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n303 SN74LS63]<!--July2018-->
|- {{anchor|7464}}
| 74x64
| 1
| 4-3-2-2输入 AND-OR-Invert gate
|
|
| 14
| [http://www.ti.com/lit/gpn/sn54s64 SN74S64]
|- {{anchor|7465}}
| 74x65
| 1
| 4-3-2-2 input AND-OR-Invert gate
|
| open-collector
| 14
| [http://www.ti.com/lit/gpn/sn54s64 SN74S65]
|- {{anchor|7467}}
| 74x67
| 1
| AND与门d J-K master-slave flip-flop, asynchronous preset and clear (improved 74L72)
|
|
| (16)
| [https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19720020596.pdf BL54L67Y]
|- {{anchor|7468}}
| 74L68
| 2
| 2个 J-K flip-flop, asynchronous clear (improved 74L73)
|
|
| (18)
| [https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19720020596.pdf BL54L68Y]
|-
| 74LS68
| 2
| 2个 4-bit decade counters
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n311 SN74LS68]<!--July2018-->
|- {{anchor|7469}}
| 74L69
| 2
| 2个 J-K flip-flop, asynchronous preset, common clock and clear
|
|
| (18)
| [https://archive.org/stream/bitsavers_derivationates1974DigitalIntegratedCircuitDataBook_79049866#page/n47 BL54L69Y]
|-
| 74LS69
| 2
| 2个 4-bit binary counters
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n311 SN74LS69]<!--July2018-->
|- {{anchor|7470}}
| 74x70
| 1
| AND-gated positive edge triggered J-K [[Flip-flop (electronics)|flip-flop]], asynchronous preset and clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n317 SN7470]<!--July2018-->
|- {{anchor|7471}}
| 74H71
| 1
| AND-OR-gated J-K master-slave flip-flop, preset
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n321 SN74H71]<!--July2018-->
|-
| 74L71
| 1
| AND-gated R-S master-slave flip-flop, preset and clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n325 SN54L71]<!--July2018-->
|- {{anchor|7472}}
| 74x72
| 1
| AND与门d J-K master-slave flip-flop, asynchronous preset and clear
|
|
| 14
| [http://www.ti.com/lit/gpn/sn5472 SN7472]<!--July2018-->
|- {{anchor|7473}}
| 74x73
| 2
| 2个 J-K flip-flop, asynchronous clear
|
|
| 14
| [http://www.ti.com/lit/gpn/sn54ls73a SN54LS73A]<!--July2018-->
|- {{anchor|7474}}
| 74x74
| 2
| 2个 D positive edge triggered flip-flop, asynchronous preset and clear
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls74a SN74LS74A]<!--July2018-->
|- {{anchor|7475}}
| 74x75
| 2
| 4-bit bistable [[latch (electronic)|latch]], complementary outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls75 SN74LS75]<!--July2018-->
|- {{anchor|7476}}
| 74x76
| 2
| 2个 J-K flip-flop, asynchronous preset and clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn54ls76a SN74LS76A]<!--July2018-->
|- {{anchor|7477}}
| 74x77
| 1
| 4-bit bistable latch
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls75 SN74LS77]<!--July2018-->
|- {{anchor|7478}}
| 74H78
| 2
| 2个 positive pulse triggered J-K flip-flop, preset, common clock and common clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n369 SN74H78]<!--July2018-->
|-
| 74L78
| 2
| 2个 positive pulse triggered J-K flip-flop, preset, common clock and common clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n369 SN54L78]<!--July2018-->
|-
| 74LS78
| 2
| 2个 negative edge triggered J-K flip-flop, preset, common clock and common clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n369 SN74LS78A]<!--July2018-->
|- {{anchor|7479}}
| 74x79
| 2
| 2个 D positive edge triggered flip-flop, asynchronous preset and clear
|
|
| 14
| [https://archive.org/details/bitsavers_motoroladaTTLIntegratedCircuitsDataBook_38442857/page/ntegrated_Circuits_Data_Book#page/n387 MC7479]
|- {{anchor|7480}}
| 74x80
| 1
| gated [[full adder]]
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n377 SN7480]<!--July2018-->
|- {{anchor|7481}}
| 74x81
| 1
| 16-bit [[random access memory|RAM]]
|
|
| 14
| [http://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036758.pdf SN7481A]
|- {{anchor|7482}}
| 74x82
| 1
| 2-bit binary full adder
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n379 SN7482]<!--July2018-->
|- {{anchor|7483}}
| 74x83
| 1
| 4-bit binary full adder
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n383 SN74LS83A]<!--July2018-->
|- {{anchor|7484}}
| 74x84
| 1
| 16-bit [[random access memory|RAM]]
|
|
| 16
| [http://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036758.pdf SN7484A]
|- {{anchor|7485}}
| 74x85
| 1
| 4-bit [[digital comparator|magnitude comparator]]
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls85 SN74LS85]<!--July2018-->
|- {{anchor|7486}}
| 74x86
| 4
| 4个 2输入 [[XOR gate]]
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls86a SN74LS86A]<!--July2018-->
|- {{anchor|7487}}
| 74x87
| 1
| 4-bit true/complement/zero/one element
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n403 SN74H87]<!--July2018-->
|- {{anchor|7488}}
| 74x88
| 1
| 256-bit [[read-only memory|ROM]] (32x8)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN7488A]<!--July2018-->
|- {{anchor|7489}}
| 74x89
| 1
| 64-bit [[random access memory|RAM]] (16x4), 4 data inputs, 4 inverted data outputs
|
| open-collector
| 16
| [http://pdf.datasheetcatalog.com/datasheets/270/499426_DS.pdf SN7489]<!--July2018-->
|- {{anchor|7490}}
| 74x90
| 1
| [[Counter (digital)#Decade counter|decade counter]] (separate divide-by-2 and divide-by-5 sections)
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls90 SN74LS90]<!--July2018-->
|- {{anchor|7491}}
| 74x91
| 1
| 8-bit [[shift register]], serial in, serial out, gated input
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n419 SN74LS91]<!--July2018-->
|- {{anchor|7492}}
| 74x92
| 1
| divide-by-12 counter (separate divide-by-2 and divide-by-6 sections)
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls92 SN74LS92]<!--July2018-->
|- {{anchor|7493}}
| 74x93
| 1
| 4-bit binary counter (separate divide-by-2 and divide-by-8 sections); different pinout for 74L93
|
|
| 14
| [https://www.datasheets360.com/pdf/7761228217550421319 SN74LS93]
|- {{anchor|7494}}
| 74x94
| 1
| 4-bit shift register, 2个 asynchronous presets
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n423 SN7494]<!--July2018-->
|- {{anchor|7495}}
| 74x95
| 1
| 4-bit shift register, parallel in, parallel out, serial input; different pinout for 74L95
|
|
| 14
| [https://www.datasheets360.com/pdf/-5053843966740530793 SN74LS95B]
|- {{anchor|7496}}
| 74x96
| 1
| 5-bit parallel-in/parallel-out shift register, asynchronous preset
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n435 SN74LS96]<!--July2018-->
|- {{anchor|7497}}
| 74x97
| 1
| synchronous 6-bit binary rate multiplier
|
|
| 16
| [http://www.ti.com/lit/gpn/sn5497 SN7497]<!--July2018-->
|- {{anchor|7498}}
| 74x98
| 1
| 4-bit data selector/storage register
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n449 SN54L98]<!--July2018-->
|- {{anchor|7499}}
| 74x99
| 1
| 4-bit bidirectional universal shift register
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n451 SN54L99]<!--July2018-->
|-
! {{TOC tab|Part number|74x100 – 74x199}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74100}}
| 74x100
| 2
| 2个 4-bit bistable latch
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n457 SN74100]
|- {{anchor|74101}}
| 74x101
| 1
| AND-OR-gated J-K negative-edge-triggered flip-flop, preset
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n459 SN74H101]
|- {{anchor|74102}}
| 74x102
| 1
| AND-gated J-K negative-edge-triggered flip-flop, preset and clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n463 SN74H102]
|- {{anchor|74103}}
| 74x103
| 2
| 2个 J-K negative-edge-triggered flip-flop, clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n465 SN74H103]
|- {{anchor|74104}}
| 74x104
| 1
| J-K master-slave flip-flop
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n469 SN74104]
|- {{anchor|74105}}
| 74x105
| 1
| J-K master-slave flip-flop, J2 and K2 inverted
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n469 SN74105]
|- {{anchor|74106}}
| 74x106
| 2
| 2个 J-K negative-edge-triggered flip-flop, preset and clear
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n471 SN74H106]
|- {{anchor|74107}}
| 74x107
| 2
| 2个 J-K flip-flop, clear
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls107a SN74107]
|-
| 74x107A
| 2
| 2个 J-K negative-edge-triggered flip-flop, clear
|
|
| 14
| [https://web.archive.org/web/20070125105009/http://focus.ti.com/lit/ds/symlink/sn74107.pdf SN74LS107A]
|- {{anchor|74108}}
| 74x108
| 2
| 2个 J-K negative-edge-triggered flip-flop, preset, common clear and common clock
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n479 SN74H108]
|- {{anchor|74109}}
| 74x109
| 2
| 2个 J-NotK positive-edge-triggered flip-flop, clear and preset
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls109a SN74109]
|- {{anchor|74110}}
| 74x110
| 1
| AND-gated J-K master-slave flip-flop, data lockout
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n487 SN74110]
|- {{anchor|74111}}
| 74x111
| 2
| 2个 J-K master-slave flip-flop, data lockout, reset, set
|
|
| 16
| [http://www.fecegypt.com/uploads/dataSheet/1481104190_tl74115n.pdf TL74111N]
|- {{anchor|74112}}
| 74x112
| 2
| 2个 J-K negative-edge-triggered flip-flop, clear and preset
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74s112a SN74LS112A]
|- {{anchor|74113}}
| 74x113
| 2
| 2个 J-K negative-edge-triggered flip-flop, preset
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n499 SN74LS113A]
|- {{anchor|74114}}
| 74x114
| 2
| 2个 J-K negative-edge-triggered flip-flop, preset, common clock and clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n505 SN74LS114A]
|- {{anchor|74115}}
| 74x115
| 2
| 2个 J-K master-slave flip-flop, data lockout, reset
|
|
| 14
| [http://www.fecegypt.com/uploads/dataSheet/1481104190_tl74115n.pdf TL74115N]
|- {{anchor|74116}}
| 74116, 74L116
| 2
| 2个 4-bit latch, clear
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n511 SN74116] <ref name=ttltb1>{{cite book |title=TTL-Taschenbuch, Teil 1 |trans-title=TTL Pocket Reference, Part 1 |language=de |publisher=IWT Verlag |place=Vaterstetten |date=1992 |isbn=3-88322-191-0}}</ref>{{rp|1-123}}
|-
| 74H116
| 1
| AND-gated J-K flip flop
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 14
| [https://archive.org/details/Digital_IC_Equivalents/page/n97 MC74H116]
|- {{anchor|74117}}
| 74x117
| 1
| AND-gated J-K flip flop, one J and K input inverted
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 14
| [https://archive.org/details/Digital_IC_Equivalents/page/n97 MC74H117]
|- {{anchor|74118}}
| 74x118
| 6
| 6个 set/reset latch, common reset
|
|
| 16
| [https://archive.org/details/bitsavers_ittdataBootorProductCatalog_54440015/page/n161 ITT74118]
|- {{anchor|74119}}
| 74119
| 6
| 6个 set/reset latch
|
|
| 24
| [https://archive.org/stream/bitsavers_derivationates1974DigitalIntegratedCircuitDataBook_79049866#page/n57 TL74119N] <ref name=ttltb1/>{{rp|1-125}}
|-
| 74H119
| 2
| 2个 J-K flip-flop, shared clear and clock inputs
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 14
| [https://archive.org/details/Digital_IC_Equivalents/page/n97 MC74H119]
|- {{anchor|74120}}
| 74120
| 2
| 2个 pulse synchronizer/drivers
| 15&nbsp;kΩ pull-up
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n515 SN74120]
|-
| 74H120
| 2
| 2个 J-K flip-flop, separate clock inputs
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 14
| [https://archive.org/details/Digital_IC_Equivalents/page/n97 MC74H120]
|- {{anchor|74121}}
| 74x121
| 1
| monostable [[multivibrator]]
| Schmitt trigger
|
| 14
| [http://www.ti.com/lit/gpn/sn74121 SN74121]
|- {{anchor|74122}}
| 74x122
| 1
| [[retriggerable monostable]] multivibrator, clear
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls122 SN74122]
|- {{anchor|74123}}
| 74x123
| 2
| 2个 retriggerable monostable multivibrator, clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls122 SN74123]
|- {{anchor|74124}}
| 74x124
| 2
| 2个 [[voltage-controlled oscillator]]
| analog
|
| 16
| [http://www.ti.com/lit/gpn/sn54s124 SN74S124]
|- {{anchor|74125}}
| 74x125
| 4
| 4个 bus buffer, negative enable
|
| [[三态逻辑|三态逻辑]]
| 14
| [http://www.ti.com/lit/gpn/sn74ls126a SN74LS125A]
|- {{anchor|74126}}
| 74x126
| 4
| 4个 bus buffer, positive enable
|
| [[三态逻辑|三态逻辑]]
| 14
| [http://www.ti.com/lit/gpn/sn74ls126a SN74LS126A]
|- {{anchor|74128}}
| 74x128
| 4
| 4个 2输入 NOR 或非门
|
| driver [[Electrical termination|50&nbsp;Ω]]
| 14
| [http://www.ti.com/lit/gpn/sn74128 SN74128]<!--July2018-->
|- {{anchor|74130}}
| 74x130
| 2
| retriggerable monostable multivibrator
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls122 SN74130]
|- {{anchor|74131}}
| 74131
| 4
| 4个 2输入 AND与门
|
| open-collector 15&nbsp;V
| 14
| [https://archive.org/details/bitsavers_ittdataBootorProductCatalog_54440015/page/n181 ITT74131]
|-
| 74AS131, 74ALS131
| 1
| 3-to-8 line decoder/demultiplexer, address register, inverting outputs
|
|
| 16
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00211615.pdf SN74AS131]
|- {{anchor|74132}}
| 74x132
| 4
| 4个 2输入 NAND与非门
| Schmitt trigger
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls132 SN74LS132]<!--July2018-->
|- {{anchor|74133}}
| 74x133
| 1
| 1个 13输入 NAND与非门
|
|
| 16
| [http://www.ti.com/lit/gpn/sn54als133 SN54ALS133]<!--July2018-->
|- {{anchor|74134}}
| 74x134
| 1
| 1个 12输入 NAND与非门
|
| [[三态逻辑|三态逻辑]]
| 16
| [http://www.ti.com/lit/gpn/sn54s134 SN74S134]
|- {{anchor|74135}}
| 74x135
| 4
| 4个 XOR异或门/XNOR异或非门, two inputs to select logic type
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n567 SN74S135]<!--July2018-->
|- {{anchor|74136}}
| 74x136
| 4
| 4个 2输入 [[XOR gate]]
|
| open-collector
| 14
| [http://www.ti.com/lit/gpn/sn74ls136 SN74LS136]<!--July2018-->
|- {{anchor|74137}}
| 74x137
| 1
| 3-to-8 line decoder/[[demultiplexer]], address latch, inverting outputs
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n573 SN74LS137]<!--July2018-->
|- {{anchor|74138}}
| 74x138
| 1
| 3-to-8 line decoder/demultiplexer, inverting outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls138 SN74LS138]<!--July2018-->
|- {{anchor|74139}}
| 74x139
| 2
| 2个 2-to-4 line decoder/demultiplexer, inverting outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls139a SN74LS139A]
|- {{anchor|74140}}
| 74x140
| 2
| 2个 4输入 NAND与非门
|
| driver 50&nbsp;Ω
| 14
| [http://www.ti.com/lit/gpn/sn54s140 SN74S140]
|- {{anchor|74141}}
| 74x141
| 1
| BCD to decimal decoder/driver for [[cold-cathode]] indicator / Nixie tube
|
| open-collector 60&nbsp;V
| 16
| [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n146 DM74141]
|- {{anchor|74142}}
| 74x142
| 1
| decade counter/latch/decoder/driver for Nixie tubes
|
| open-collector 60&nbsp;V
| 16
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n137 SN74142]
|- {{anchor|74143}}
| 74x143
| 1
| decade counter/latch/decoder/7-segment driver
|
| constant current 15&nbsp;mA
| 24
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n141 SN74143]
|- {{anchor|74144}}
| 74x144
| 1
| decade counter/latch/decoder/7-segment driver
|
| open-collector 15&nbsp;V / 25&nbsp;mA
| 24
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n141 SN74144]
|- {{anchor|74145}}
| 74x145
| 1
| BCD to decimal decoder/driver
|
| open-collector 15&nbsp;V / 80&nbsp;mA
| 16
| [http://www.ti.com/lit/gpn/sn74ls145 SN74145]
|- {{anchor|74146}}
| 74x146
| 1
| 3-to-8 line decoder
|
|
| {{Unknown|{{sp}}}}
| [https://archive.org/details/bitsavers_motoroladaTTLIntegratedCircuitsDataBook_38442857/page/ntegrated_Circuits_Data_Book#page/n77 MCE74H146]
|- {{anchor|74147}}
| 74x147
| 1
| 10-line to 4-line priority encoder
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls148 SN74147]
|- {{anchor|74148}}
| 74x148
| 1
| 8-line to 3-line priority encoder
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls148 SN74148]
|- {{anchor|74149}}
| 74x149
| 1
| 8-line to 8-line priority encoder
|
|
| 20
| [http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005364.PDF MM74HCT149]
|- {{anchor|74150}}
| 74x150
| 1
| 16-line to 1-line data selector/[[multiplexer]]
|
|
| 24
| [http://www.ti.com/lit/gpn/sn74ls151 SN74150]
|- {{anchor|74151}}
| 74x151
| 1
| 8-line to 1-line data selector/multiplexer
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls151 SN74151A]
|- {{anchor|74152}}
| 74x152
| 1
| 8-line to 1-line data selector/multiplexer, inverting output
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n611 SN54152A]
|- {{anchor|74153}}
| 74x153
| 2
| 2个 4-line to 1-line data selector/multiplexer, non-inverting outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls153 SN74153]
|- {{anchor|74154}}
| 74x154
| 1
| 4-to-16 line decoder/demultiplexer, inverting outputs
|
|
| 24
| [https://web.archive.org/web/20150321045049/http://www.ti.com/lit/ds/symlink/sn74154.pdf SN74154]
|- {{anchor|74155}}
| 74x155
| 2
| 2个 2-to-4 line decoder/demultiplexer, inverting outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls155a SN74155]
|- {{anchor|74156}}
| 74x156
| 2
| 2个 2-to-4 line decoder/demultiplexer, inverting outputs
|
| open-collector
| 16
| [http://www.ti.com/lit/gpn/sn74ls155a SN74156]
|- {{anchor|74157}}
| 74x157
| 4
| 4个 2-line to 1-line data selector/multiplexer, non-inverting outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls157 SN74157]
|- {{anchor|74158}}
| 74x158
| 4
| 4个 2-line to 1-line data selector/multiplexer, inverting outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls157 SN74LS158]
|- {{anchor|74159}}
| 74x159
| 1
| 4-to-16 line decoder/demultiplexer
|
| open-collector
| 24
| [https://web.archive.org/web/20070102021404/http://focus.ti.com/lit/ds/symlink/sn74159.pdf SN74159]
|- {{anchor|74160}}
| 74x160
| 1
| synchronous presettable 4-bit decade counter, asynchronous clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls161a SN74160]
|- {{anchor|74161}}
| 74x161
| 1
| synchronous presettable 4-bit binary counter, asynchronous clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls161a SN74161]
|- {{anchor|74162}}
| 74x162
| 1
| synchronous presettable 4-bit decade counter, synchronous clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls161a SN74162]
|- {{anchor|74163}}
| 74x163
| 1
| synchronous presettable 4-bit binary counter, synchronous clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls161a SN74163]
|- {{anchor|74164}}
| 74x164
| 1
| 8-bit serial-in parallel-out ([[Shift_register#Serial-in_parallel-out_(SIPO)|SIPO]]) shift register, asynchronous clear, not output latch
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls164 SN74164]
|- {{anchor|74165}}
| 74x165
| 1
| 8-bit parallel-in serial-out ([[Shift_register#Parallel-in_serial-out_(PISO)|PISO]]) shift register, parallel load, complementary outputs
|
|
| 16
| [http://www.ti.com/lit/ds/symlink/sn54hc165.pdf SN74165]
|- {{anchor|74166}}
| 74x166
| 1
| parallel-load 8-bit shift register
|
|
| 16
| [http://www.ti.com/lit/gpn/sn54ls166a SN74166]
|- {{anchor|74167}}
| 74x167
| 1
| synchronous decade rate multiplier
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n695 SN74167]
|- {{anchor|74168}}
| 74x168
| 1
| synchronous presettable 4-bit up/down decade counter
|
|
| 16
| [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n229 DM74LS168]
|- {{anchor|74169}}
| 74x169
| 1
| synchronous presettable 4-bit up/down binary counter
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls169b SN74LS169B]
|- {{anchor|74170}}
| 74x170
| 1
| 16-bit register file (4x4)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n715 SN74170]
|- {{anchor|74171}}
| 74x171
| 4
| 4个 D flip-flops, clear
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n725 SN74LS171]
|- {{anchor|74172}}
| 74x172
| 1
| 16-bit multiple port register file (8x2)
|
| [[三态逻辑|三态逻辑]]
| 24
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n729 SN74172]
|- {{anchor|74173}}
| 74x173
| 4
| 4个 D flip-flop, asynchronous clear
|
| [[三态逻辑|三态逻辑]]
| 16
| [http://www.ti.com/lit/gpn/sn54ls173a SN74173]
|- {{anchor|74174}}
| 74x174
| 6
| 6个 D flip-flop, common asynchronous clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74s175 SN74174]
|- {{anchor|74175}}
| 74x175
| 4
| 4个 D edge-triggered flip-flop, complementary outputs and asynchronous clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74s175 SN74175]
|- {{anchor|74176}}
| 74x176
| 1
| presettable decade (bi-quinary) counter/latch
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n745 SN74176]
|- {{anchor|74177}}
| 74x177
| 1
| presettable binary counter/latch
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n745 SN74177]
|- {{anchor|74178}}
| 74x178
| 1
| 4-bit parallel-access shift register
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n751 SN74178]
|- {{anchor|74179}}
| 74x179
| 1
| 4-bit parallel-access shift register, asynchronous clear input, complementary Q<sub>d</sub> output
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n751 SN74179]
|- {{anchor|74180}}
| 74x180
| 1
| 9-bit odd/even [[parity bit]] generator and checker
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n755 SN74180]
|- {{anchor|74181}}
| <!--pn-->[[74181|74x181]]
| 1
| 4-bit arithmetic logic unit and function generator
|
|
| 24
| [http://www.ti.com/lit/gpn/sn54ls181 SN74LS181]
|- {{anchor|74182}}
| 74x182
| 1
| lookahead carry generator
|
|
| 16
| [https://web.archive.org/web/20160418004301/http://www.ti.com/lit/ds/symlink/sn74s182.pdf SN74S182]
|- {{anchor|74183}}
| 74x183
| 2
| 2个 carry-save [[full adder]]
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n777 SN74LS183]
|- {{anchor|74184}}
| 74x184
| 1
| BCD to binary converter
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n781 SN74184]
|- {{anchor|74185}}
| 74x185
| 1
| 6-bit binary to BCD converter
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n781 SN74185A]
|- {{anchor|74186}}
| 74x186
| 1
| 512-bit [[read-only memory|ROM]] (64x8)
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n121 SN74186]
|- {{anchor|74187}}
| 74x187
| 1
| 1024-bit [[read-only memory|ROM]] (256x4)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74187]
|- {{anchor|74188}}
| 74x188
| 1
| 256-bit [[programmable read-only memory|PROM]] (32x8)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S188]
|- {{anchor|74189}}
| 74x189
| 1
| 64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n191 SN74S189]
|- {{anchor|74190}}
| 74x190
| 1
| synchronous presettable up/down 4-bit decade counter
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls191 SN74190]
|- {{anchor|74191}}
| 74x191
| 1
| synchronous presettable up/down 4-bit binary counter
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls191 SN74191]
|- {{anchor|74192}}
| 74x192
| 1
| synchronous presettable up/down 4-bit decade counter, clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls193 SN74192]
|- {{anchor|74193}}
| 74x193
| 1
| synchronous presettable up/down 4-bit binary counter, clear
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls193 SN74193]
|- {{anchor|74194}}
| 74x194
| 1
| 4-bit bidirectional universal shift register
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n820 SN74194]<!--December2019-->
|- {{anchor|74195}}
| 74x195
| 1
| 4-bit parallel-access shift register
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n829 SN74195]
|- {{anchor|74196}}
| 74x196
| 1
| presettable 4-bit decade counter/latch
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n837 SN74196]
|- {{anchor|74197}}
| 74x197
| 1
| presettable 4-bit binary counter/latch
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n837 SN74197]
|- {{anchor|74198}}
| 74x198
| 1
| 8-bit bidirectional universal shift register
|
|
| 24
| [https://web.archive.org/web/20070228042947/http://focus.ti.com/lit/ds/symlink/sn74198.pdf SN74198]
|- {{anchor|74199}}
| 74x199
| 1
| 8-bit universal shift register, J-NotK serial inputs
|
|
| 24
| [https://web.archive.org/web/20070228042947/http://focus.ti.com/lit/ds/symlink/sn74198.pdf SN74199]
|-
! {{TOC tab|Part number|74x200 – 74x299}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74200}}
| 74x200
| 1
| 256-bit RAM (256x1)
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n299 DM74S200]
|- {{anchor|74201}}
| 74x201
| 1
| 256-bit RAM (256x1)
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n195 SN74S201]
|- {{anchor|74202}}
| 74x202
| 1
| 256-bit RAM (256x1) with power down
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBook2ed05_2617547/page/n51 SN74LS202]
|- {{anchor|74206}}
| 74x206
| 1
| 256-bit RAM (256x1)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n301 DM74S206]
|- {{anchor|74207}}
| 74x207
| 1
| 1024-bit RAM (256x4)
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS207]
|- {{anchor|74208}}
| 74x208
| 1
| 1024-bit RAM (256x4), separate data in- and outputs
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS208]
|- {{anchor|74209}}
| 74x209
| 1
| 1024-bit RAM (1024x1)
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookmoryDataBook1975_9924035/page/nductor_Memory_Data_Book_1975#page/n171 SN74S209]
|- {{anchor|74210}}
| 74x210
| 8
| 8个 buffer, inverting
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n311 SN74LS210]
|- {{anchor|74211}}
| 74x211
| 1
| 144-bit RAM (16x9) with output latch
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n181 74F211]
|- {{anchor|74212}}
| 74x212
| 1
| 144-bit RAM (16x9)
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n185 74F212]
|- {{anchor|74213}}
| 74x213
| 1
| 192-bit RAM (16x12)
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n189 74F213]
|- {{anchor|74214}}
| 74x214
| 1
| 1024-bit RAM (1024x1)
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS214]
|- {{anchor|74215}}
| 74x215
| 1
| 1024-bit RAM (1024x1) with power-down mode
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS215]
|- {{anchor|74216}}
| 74x216
| 1
| 256-bit RAM (64x4), common I/O
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044696.pdf SN74LS216]
|- {{anchor|74217}}
| 74x217
| 1
| 256-bit RAM (64x4)
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS217]
|- {{anchor|74218}}
| 74x218
| 1
| 256-bit RAM (32x8)
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS218]
|- {{anchor|74219}}
| 74x219
| 1
| 64-bit RAM (16x4), non-inverting outputs
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/stream/SupplementToTheTTLDataBookForDesignEngineers2ndEdition/Supplement%20to%20The%20TTL%20Data%20Book%20for%20Design%20Engineers_2nd_Edition#page/n5 SN74LS219]
|- {{anchor|74221}}
| 74x221
| 2
| 2个 monostable multivibrator
| Schmitt trigger
|
| 16
| [http://www.ti.com/lit/gpn/sn74221 SN74221]
|- {{anchor|74222}}
| 74x222
| 1
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous, input/output ready enable
|
| [[三态逻辑|三态逻辑]]
| 20
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS222]
|- {{anchor|74224}}
| 74x224
| 1
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous
|
| [[三态逻辑|三态逻辑]]
| 16
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS224]
|- {{anchor|74225}}
| 74x225
| 1
| 80-bit FIFO memory (16x5), asynchronous
|
| [[三态逻辑|三态逻辑]]
| 20
| [http://www.ti.com/lit/gpn/sn74s225 SN74S225]
|- {{anchor|74226}}
| 74x226
| 1
| 4-bit parallel latched bus transceiver
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n219 SN74S226]
|- {{anchor|74227}}
| 74x227
| 1
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous, input/output ready enable
|
| open-collector
| 20
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS727]
|- {{anchor|74228}}
| 74x228
| 1
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous
|
| open-collector
| 20
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS728]
|- {{anchor|74229}}
| 74x229
| 1
| 80-bit FIFO memory (16x5), asynchronous
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://web.archive.org/web/20070101063514/http://focus.ti.com/lit/ds/symlink/sn74als229b.pdf SN74ALS229B]
|- {{anchor|74230}}
| 74x230
| 2
| 2个 4-bit buffer/driver, one inverted, one non-inverted; negative enable
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS230]
|- {{anchor|74231}}
| 74x231
| 2
| 2个 4-bit buffer/driver, both inverted; one positive and one negative enable
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS231]
|- {{anchor|74232}}
| 74x232
| 1
| 64-bit FIFO memory (16x4), asynchronous
|
| [[三态逻辑|三态逻辑]]
| 16
| [http://www.ti.com/lit/gpn/sn74als232b SN74ALS232B]
|- {{anchor|74233}}
| 74x233
| 1
| 80-bit FIFO memory (16x5), asynchronous
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n101 SN74ALS233B]
|- {{anchor|74234}}
| 74x234
| 1
| 256-bit FIFO memory (64x4), asynchronous
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n63 SN74ALS234]
|- {{anchor|74235}}
| 74x235
| 1
| 320-bit FIFO memory (64x5), asynchronous
|
| [[三态逻辑|三态逻辑]]
| 20
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n109 SN74ALS235]
|- {{anchor|74236}}
| 74x236
| 1
| 256-bit FIFO memory (64x4), asynchronous
|
| [[三态逻辑|三态逻辑]]
| 16
| [https://web.archive.org/web/20070102044700/http://focus.ti.com/lit/ds/symlink/sn74als236.pdf SN74ALS236]
|- {{anchor|74237}}
| 74x237
| 1
| 3-to-8 line decoder/demultiplexer, address latch, active high outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/cd54hc237 CD74HC237]
|- {{anchor|74238}}
| 74x238
| 1
| 3-to-8 line decoder/demultiplexer, active high outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/CD74HC238 CD74HC238]
|- {{anchor|74239}}
| 74x239
| 2
| 2个 2-to-4 line decoder/demultiplexer, active high outputs
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n241 SN74HC239]
|- {{anchor|74240}}
| 74x240
| 8
| 8个 buffer, inverting outputs
| Schmitt trigger
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS240]
|- {{anchor|74241}}
| 74x241
| 8
| 8个 buffer, non-inverting outputs
| Schmitt trigger
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS241]
|- {{anchor|74242}}
| 74x242
| 4
| 4个 bus transceiver, inverting outputs
| Schmitt trigger
| 三态逻辑
| 14
| [https://web.archive.org/web/20040608202058/http://focus.ti.com/lit/ds/symlink/sn74ls242.pdf SN74LS242]
|- {{anchor|74243}}
| 74x243
| 4
| 4个 bus transceiver, non-inverting outputs
| Schmitt trigger
| 三态逻辑
| 14
| [http://www.ti.com/lit/gpn/sn74ls243 SN74LS243]
|- {{anchor|74244}}
| 74x244
| 8
| 8个 buffer, non-inverting outputs
| Schmitt trigger
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS244]
|- {{anchor|74245}}
| 74x245
| 8
| 8个 bus transceiver, non-inverting outputs
| Schmitt trigger
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls245 SN74LS245]
|- {{anchor|74246}}
| 74x246
| 1
| BCD to 7-segment decoder/driver
|
| open-collector 30&nbsp;V
| 16
| [http://www.ti.com/lit/gpn/sn74ls247 SN74246]
|- {{anchor|74247}}
| 74x247
| 1
| BCD to 7-segment decoder/driver
|
| open-collector 15&nbsp;V
| 16
| [http://www.ti.com/lit/gpn/sn74ls247 SN74247]
|- {{anchor|74248}}
| 74x248
| 1
| BCD to 7-segment decoder/driver
|
| open-collector, 2&nbsp;kΩ pull-up
| 16
| [http://www.ti.com/lit/gpn/sn74ls247 SN74248]
|- {{anchor|74249}}
| 74x249
| 1
| BCD to 7-segment decoder/driver
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n879 SN74249]
|- {{anchor|74250}}
| 74x250
| 1
| 1 of 16 data selector/multiplexer
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n273 SN74AS250]
|- {{anchor|74251}}
| 74x251
| 1
| 8-line to 1-line data selector/multiplexer, complementary outputs
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn74ls251 SN74251]
|- {{anchor|74253}}
| 74x253
| 2
| 2个 4-line to 1-line data selector/multiplexer
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn74ls253 SN74LS253]
|- {{anchor|74255}}
| 74x255
| 2
| 2个 2-to-4 line decoder/demultiplexer, inverting outputs
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_icMaster19_198675341/page/n315 74LS255]
|- {{anchor|74256}}
| 74x256
| 2
| 2个 4-bit addressable latch
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n161 MC74F256]
|- {{anchor|74257}}
| 74x257
| 4
| 4个 2-line to 1-line data selector/multiplexer, non-inverting outputs
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn74ls257b SN74LS257B]
|- {{anchor|74258}}
| 74x258
| 4
| 4个 2-line to 1-line data selector/multiplexer, inverting outputs
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn74ls257b SN74LS258B]
|- {{anchor|74259}}
| 74x259
| 1
| 8-bit bit addressable input latch with clr
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls259b SN74259]
|- {{anchor|74260}}
| 74x260
| 2
| 2个 5输入 NOR 或非门
|
|
| 14
| [http://pdf.datasheetcatalog.com/datasheets/90/488420_DS.pdf SN74LS260]<!--July2018-->
|- {{anchor|74261}}
| 74x261
| 1
| 2-bit by 4-bit parallel binary multiplier
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n921 SN74LS261]<!--July2018-->
|- {{anchor|74262}}
| 74x262
| 1
| 5760-bit ROM ([[Teletext]] character set, 128 characters 5x9)
|
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044628.pdf SN74S262N]
|- {{anchor|74264}}
| 74x264
| 1
| look ahead carry generator
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n295 SN74AS264]
|- {{anchor|74265}}
| 74x265
| 4
| 4个 complementary output elements
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n927 SN74265]<!--July2018-->
|- {{anchor|74266}}
| 74x266
| 4
| 4个 2输入 [[XNOR异或非门]]
|
| open-collector
| 14
| [http://www.ti.com/lit/gpn/sn74ls266 SN74LS266]<!--July2018-->
|- {{anchor|74268}}
| 74x268
| 6
| 6个 D-type latches, common output control, common enable
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n935 SN74S268]
|- {{anchor|74269}}
| 74x269
| 1
| 8-bit bidirectional binary counter
|
|
| 24
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n175 MC74F269]
|- {{anchor|74270}}
| 74x270
| 1
| 2048-bit [[read-only memory|ROM]] (512x4)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S270]
|- {{anchor|74271}}
| 74x271
| 1
| 2048-bit [[read-only memory|ROM]] (256x8)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S271]
|- {{anchor|74273}}
| 74x273
| 1
| 8-bit register, asynchronous clear
|
|
| 20
| [http://www.ti.com/lit/gpn/sn74ls273 SN74273]
|- {{anchor|74274}}
| 74x274
| 1
| 4-bit by 4-bit binary multiplier
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S274]
|- {{anchor|74275}}
| 74x275
| 1
| 7-bit slice [[Wallace tree]]
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S275]
|- {{anchor|74276}}
| 74x276
| 4
| 4个 J-NotK edge-triggered [[Flip-flop (electronics)|flip-flop]]s, separate clocks, common preset and clear
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n941 SN74276]
|- {{anchor|74278}}
| 74x278
| 1
| 4-bit cascadeable priority registers, latched data inputs
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n945 SN74278]
|- {{anchor|74279}}
| 74x279
| 4
| 4个 set-reset latch
|
|
| 16
| [http://www.ti.com/lit/gpn/sn54ls279a SN74279]
|- {{anchor|74280}}
| 74x280
| 1
| 9-bit odd/even [[parity bit]] generator/checker
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls280 SN74LS280]
|- {{anchor|74281}}
| 74x281
| 1
| 4-bit parallel binary accumulator
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n959 SN74S281]
|- {{anchor|74282}}
| 74x282
| 1
| look-ahead carry generator, selectable carry inputs
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n309 SN74AS282]
|- {{anchor|74283}}
| 74x283
| 1
| 4-bit binary [[full adder]] (has carry in function)
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls283 SN74283]
|- {{anchor|74284}}
| 74x284
| 1
| 4-bit by 4-bit parallel binary multiplier (low order 4 bits of product)
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n971 SN74284]
|- {{anchor|74285}}
| 74x285
| 1
| 4-bit by 4-bit parallel binary multiplier (high order 4 bits of product)
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n971 SN74285]
|- {{anchor|74286}}
| 74x286
| 1
| 9-bit parity generator/checker, bus driver parity I/O port
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74as286 SN74AS286]
|- {{anchor|74287}}
| 74x287
| 1
| 1024-bit [[programmable read-only memory|PROM]] (256x4)
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S287]
|- {{anchor|74288}}
| 74x288
| 1
| 256-bit [[programmable read-only memory|PROM]] (32x8)
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S288]
|- {{anchor|74289}}
| 74x289
| 1
| 64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n191 SN74S289]
|- {{anchor|74290}}
| 74x290
| 1
| decade counter (separate divide-by-2 and divide-by-5 sections)
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls293 SN74290]
|- {{anchor|74292}}
| 74x292
| 1
| programmable frequency divider/digital timer
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls292 SN74LS292]
|- {{anchor|74293}}
| 74x293
| 1
| 4-bit binary counter (separate divide-by-2 and divide-by-8 sections)
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls293 SN74293]
|- {{anchor|74294}}
| 74x294
| 1
| programmable frequency divider/digital timer
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls292 SN74LS294]
|- {{anchor|74295}}
| 74x295
| 1
| 4-bit bidirectional shift register
|
| 三态逻辑
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n989 SN74LS295B]
|- {{anchor|74297}}
| 74x297
| 1
| digital [[phase-locked loop]] filter
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls297 SN74LS297]
|- {{anchor|74298}}
| 74x298
| 4
| 4个 2输入 multiplexer, storage
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls298 SN74298]
|- {{anchor|74299}}
| 74x299
| 1
| 8-bit bidirectional universal shift/storage register
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls299 SN74LS299]
|-
! {{TOC tab|Part number|74x300 – 74x399}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74300}}
| 74x300
| 1
| 256-bit [[random access memory|RAM]] (256x1)
|
| open-collector
| 16
| [https://archive.org/details/TexasInstruments-TI-Data-TheTTLDataBookforDesignEngineersSecondEditionOCR/page/n135 SN74LS300A]
|- {{anchor|74301}}
| 74x301
| 1
| 256-bit [[random access memory|RAM]] (256x1)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n195 SN74S301]
|- {{anchor|74302}}
| 74x302
| 1
| 256-bit RAM (256x1)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBook2ed05_2617547/page/n63 SN74LS302]
|- {{anchor|74303}}
| 74x303
| 1
| 8个 divide-by-2 clock driver, 2 outputs inverted
|
|
| 16
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n515 SN74AS303]
|- {{anchor|74304}}
| 74x304
| 1
| 8个 divide-by-2 clock driver
|
|
| 16
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n517 SN74AS304]
|- {{anchor|74305}}
| 74x305
| 1
| 8个 divide-by-2 clock driver, 4 outputs inverted
|
|
| 16
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n521 SN74AS305]
|- {{anchor|74309}}
| 74x309
| 1
| 1024-bit RAM (1024x1)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookmoryDataBook1975_9924035/page/nductor_Memory_Data_Book_1975#page/n171 SN74S309]
|- {{anchor|74310}}
| 74x310
| 8
| 8个 buffer, inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n315 SN74LS310]
|- {{anchor|74311}}
| 74x311
| 1
| 144-bit RAM (16x9) with output latch
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_20099339/page/n303 74F311]
|- {{anchor|74312}}
| 74x312
| 1
| 144-bit RAM (16x9)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_20099339/page/n303 74F312]
|- {{anchor|74313}}
| 74x313
| 1
| 192-bit RAM (16x12)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_20099339/page/n303 74F313]
|- {{anchor|74314}}
| 74x314
| 1
| 1024-bit RAM (1024x1)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS314]
|- {{anchor|74315}}
| 74x315
| 1
| 1024-bit RAM (1024x1) with power-down mode
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS315]
|- {{anchor|74316}}
| 74x316
| 1
| 256-bit RAM (64x4), common I/O
|
| open-collector
| 16
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044696.pdf SN74LS316]
|- {{anchor|74317}}
| 74x317
| 1
| 256-bit RAM (64x4)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n221 SN74ALS317]
|- {{anchor|74318}}
| 74x318
| 1
| 256-bit RAM (32x8)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n221 SN74ALS318]
|- {{anchor|74319}}
| 74x319
| 1
| 64-bit [[random access memory|RAM]] (16x4)
|
| open-collector
| 16
| [https://archive.org/stream/SupplementToTheTTLDataBookForDesignEngineers2ndEdition/Supplement%20to%20The%20TTL%20Data%20Book%20for%20Design%20Engineers_2nd_Edition#page/n5 SN74LS319]
|- {{anchor|74320}}
| 74x320
| 1
| crystal-controlled [[crystal oscillator|oscillator]]
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1013 SN74LS320]
|- {{anchor|74321}}
| 74x321
| 1
| crystal-controlled oscillators, F/2 and F/4 count-down outputs
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1013 SN74LS320]
|- {{anchor|74322}}
| 74x322
| 1
| 8-bit shift register, sign extend
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1013 SN74LS322A]
|- {{anchor|74323}}
| 74x323
| 1
| 8-bit bidirectional universal shift/storage register, synchronous clear
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls323 SN74LS323]
|- {{anchor|74324}}
| 74x324
| 1
| voltage-controlled oscillator (or crystal controlled), enable input, complementary outputs
| analog
|
| 14
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n443 SN74LS324]
|- {{anchor|74325}}
| 74x325
| 2
| 2个 voltage-controlled oscillator (or crystal controlled), complementary outputs
| analog
|
| 16
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n443 SN74LS325]
|- {{anchor|74326}}
| 74x326
| 2
| 2个 voltage-controlled oscillator (or crystal controlled), enable input, complementary outputs
| analog
|
| 16
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n443 SN74LS326]
|- {{anchor|74327}}
| 74x327
| 2
| 2个 voltage-controlled oscillator (or crystal controlled)
| analog
|
| 14
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n443 SN74LS327]
|- {{anchor|74330}}
| 74x330
| 1
| [[programmable logic array|PLA]] (12 inputs, 50 terms, 6 outputs)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n231 SN74S330]
|- {{anchor|74331}}
| 74x331
| 1
| [[programmable logic array|PLA]] (12 inputs, 50 terms, 6 outputs)
|
| open-collector, 2.5&nbsp;kΩ pull-up
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n231 SN74S331]
|- {{anchor|74333}}
| 74x333
| 1
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs, 4 state registers)
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS333]
|- {{anchor|74334}}
| 74x334
| 1
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs)
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS334]
|- {{anchor|74335}}
| 74x335
| 1
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs, 4 state registers)
|
| open-collector
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS335]
|- {{anchor|74336}}
| 74x336
| 1
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs)
|
| open-collector
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS336]
|- {{anchor|74337}}
| 74x337
| 1
| clock driver
|
| 三态逻辑
| 20
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n485 SN74ABT337]
|- {{anchor|74340}}
| 74x340
| 8
| 8个 buffer, inverting outputs
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S340]
|- {{anchor|74341}}
| 74x341
| 8
| 8个 buffer, non-inverting outputs
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S341]
|- {{anchor|74344}}
| 74x344
| 8
| 8个 buffer, non-inverting outputs
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S344]
|- {{anchor|74347}}
| 74x347
| 1
| BCD to 7-segment decoders/drivers, low voltage version of 7447
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1027 SN74LS347]
|- {{anchor|74348}}
| 74x348
| 1
| 8 to 3-line priority encoder
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn74ls348 SN74LS348]
|- {{anchor|74350}}
| 74x350
| 1
| 4-bit shifter
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1035 SN74S350]
|- {{anchor|74351}}
| 74x351
| 2
| 2个 8-line to 1-line data selectors/multiplexers, 4 common data inputs
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1041 SN74351]
|- {{anchor|74352}}
| 74x352
| 2
| 2个 4-line to 1-line data selectors/multiplexers, inverting outputs
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1045 SN74LS352]
|- {{anchor|74353}}
| 74x353
| 2
| 2个 4-line to 1-line data selectors/multiplexers, inverting outputs
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1047 SN74LS353]
|- {{anchor|74354}}
| 74x354
| 1
| 8-line to 1-line data selector/multiplexer, transparent registers
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/cd54hc354 CD74HC354]
|- {{anchor|74355}}
| 74x355
| 1
| 8-line to 1-line data selector/multiplexer, transparent registers
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1051 SN74LS355]
|- {{anchor|74356}}
| 74x356
| 1
| 8-line to 1-line data selector/multiplexer, edge-triggered registers
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/cd74hct356 CD74HCT356]
|- {{anchor|74357}}
| 74x357
| 1
| 8-line to 1-line data selector/multiplexer, edge-triggered registers
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1051 SN74LS357]
|- {{anchor|74361}}
| 74x361
| 1
| [[bubble memory]] function timing generator
|
|
| 22
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-X2/DSA848000-290.pdf SN74LS361]
|- {{anchor|74362}}
| 74x362
| 1
| [[clock signal#4-phase clock|four-phase clock]] generator/driver for [[Texas Instruments TMS9900]]
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n457 SN74LS362]
|- {{anchor|74363}}
| 74x363
| 1
| 8个 transparent latch
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS363]
|- {{anchor|74364}}
| 74x364
| 1
| 8个 edge-triggered D-type register
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS364]
|- {{anchor|74365}}
| 74x365
| 6
| 6个 buffer, non-inverting outputs
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS365A]
|- {{anchor|74366}}
| 74x366
| 6
| 6个 buffer, inverting outputs
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/ds/symlink/sn54hc366.pdf SN74HC366]
|- {{anchor|74367}}
| 74x367
| 6
| 6个 buffer, non-inverting outputs
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS367A]
|- {{anchor|74368}}
| 74x368
| 6
| 6个 buffer, inverting outputs
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS368A]
|- {{anchor|74370}}
| 74x370
| 1
| 2048-bit [[read-only memory|ROM]] (512x4)
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S370]
|- {{anchor|74371}}
| 74x371
| 1
| 2048-bit [[read-only memory|ROM]] (256x8)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S371]
|- {{anchor|74373}}
| 74x373
| 8
| 8个 transparent latch
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls373 SN74LS373]
|- {{anchor|74374}}
| 74x374
| 8
| 8个 register
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls373 SN74LS374]
|- {{anchor|74375}}
| 74x375
| 4
| 4个 bistable latch
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls375 SN74LS375]
|- {{anchor|74376}}
| 74x376
| 4
| 4个 J-NotK flip-flop, common clock and common clear
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1081 SN74376]
|- {{anchor|74377}}
| 74x377
| 1
| 8-bit register, clock enable
|
|
| 20
| [http://www.ti.com/lit/gpn/sn74ls377 SN74LS377]
|- {{anchor|74378}}
| 74x378
| 1
| 6-bit register, clock enable
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls377 SN74LS378]
|- {{anchor|74379}}
| 74x379
| 1
| 4-bit register, clock enable and complementary outputs
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls377 SN74LS379]
|- {{anchor|74380}}
| 74x380
| 1
| 8-bit multifunction register (combines features of x374, x377, x273, x534 ICs)
|
| 三态逻辑
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n193 SN74LS380]
|- {{anchor|74381}}
| 74x381
| 1
| 4-bit arithmetic logic unit/function generator, generate and propagate outputs
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1087 SN74LS381A]
|- {{anchor|74382}}
| 74x382
| 1
| 4-bit arithmetic logic unit/function generator, ripple carry and overflow outputs
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1087 SN74LS382]
|- {{anchor|74383}}
| 74x383
| 1
| 8-bit register
|
| open-collector
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n433 SN74S383]
|- {{anchor|74384}}
| 74x384
| 1
| 8-bit by 1-bit two's complement multipliers
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1095 SN74LS384]
|- {{anchor|74385}}
| 74x385
| 4
| 4个 serial adder/subtractor
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1099 SN74LS385]
|- {{anchor|74386}}
| 74x386
| 4
| 4个 2输入 [[XOR gate]]
|
|
| 14
| [http://pdf.datasheetcatalog.com/datasheet/motorola/SN74LS386N.pdf SN74LS386]<!--July2018-->
|- {{anchor|74387}}
| 74x387
| 1
| 1024-bit [[programmable read-only memory|PROM]] (256x4)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S387]
|- {{anchor|74388}}
| 74x388
| 1
| 4-bit D-type register
|
| 三态逻辑 and standard
| 16
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-000/Scans-0017104.pdf Am74S388]
|- {{anchor|74390}}
| 74x390
| 2
| 2个 4-bit decade counter
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls390 SN74LS390]
|- {{anchor|74393}}
| 74x393
| 2
| 2个 4-bit binary counter
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls390 SN74LS393]
|- {{anchor|74395}}
| 74x395
| 1
| 4-bit cascadable shift register
|
| 三态逻辑
| 16
| [https://web.archive.org/web/20070101063359/http://focus.ti.com/lit/ds/symlink/sn74ls395a.pdf SN74LS395A]
|- {{anchor|74396}}
| 74x396
| 8
| 8个 storage registers, parallel access
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1119 SN74LS396]
|- {{anchor|74398}}
| 74x398
| 4
| 4个 2输入 multiplexers, storage and complementary outputs
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1119 SN74LS398]
|- {{anchor|74399}}
| 74x399
| 4
| 4个 2输入 multiplexer, storage
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls399 SN74LS399]
|-
! {{TOC tab|Part number|74x400 – 74x499}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74401}}
| 74x401
| 1
| CRC generator/checker
|
|
| 14
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n371 74F401]
|- {{anchor|74402}}
| 74x402
| 1
| serial data polynomial generator/checker
|
|
| 16
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n375 74F402]
|- {{anchor|74403}}
| 74x403
| 1
| 64-bit FIFO memory (16x4)
|
| 三态逻辑
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n383 74F403]
|- {{anchor|74405}}
| 74x405
| 1
| 3-to-8 line decoder (equivalent to Intel 8205)
|
|
| 16
| [http://pdf.datasheetcatalog.com/datasheet/CEMI/mXyztyxt.pdf UCY74S405]
|- {{anchor|74406}}
| 74x406
| 1
| 3-to-8 line decoder
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 14
| [https://archive.org/details/Digital_IC_Equivalents/page/n113 MC74406P]
|- {{anchor|74407}}
| 74x407
| 1
| data access register
|
| 三态逻辑
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n401 74F407]
|- {{anchor|74408}}
| 74408
| 1
| 8-bit parity tree
|
|
| 14
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n407 MC74408]
|-
| 74S408
| 1
| controller/driver for 16k/64k/256k dRAM
|
|
| 48
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n273 SN74S408]
|- {{anchor|74409}}
| 74x409
| 1
| controller/driver for 16k/64k/256k dRAM
|
|
| 48
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n291 SN74S409]
|- {{anchor|74410}}
| 74x410
| 1
| 64-bit RAM (16x4) with output register
|
| 三态逻辑
| 18
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n407 74F410]
|- {{anchor|74411}}
| 74x411
| 1
| FIFO RAM controller
|
|
| 40
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n357 74F411]
|- {{anchor|74412}}
| 74x412
| 1
| multi-mode buffered 8-bit latches (equivalent to Intel [[Intel 3000|3212]]/8212)
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n247 SN74S412]
|- {{anchor|74413}}
| 74x413
| 1
| 256-bit FIFO memory (64x4)
|
|
| 16
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n417 74F413]
|- {{anchor|74414}}
| 74x414
| 1
| interrupt priority controller for [[Intel 8080]] (equivalent to Intel 8214)
|
|
| 24
| [http://pdf.datasheetcatalog.com/datasheet/CEMI/mXyztyxr.pdf UCY74S414]
|- {{anchor|74416}}
| 74416
| 1
| modulo 10 counter, preload and clear inputs
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n409 MC74416]
|-
| 74S416
| 1
| 4-bit bidirectional bus transceiver, non-inverting (equivalent to Intel 8216)
|
| 三态逻辑
| 16
| [http://pdf.datasheetcatalog.com/datasheet/CEMI/mXyztyxq.pdf UCY74S416]
|- {{anchor|74417}}
| 74x417
| 2
| modulo 2 and modulo 5 counters, common preload and clear inputs
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n409 MC74417]
|- {{anchor|74418}}
| 74418
| 1
| modulo 16 counter, preload and clear inputs
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n409 MC74418]
|-
| 74F418
| 1
| 32-bit error detection and correction circuit
|
| 三态逻辑
| 48
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n375 74F418]
|- {{anchor|74419}}
| 74419
| 2
| 2个 modulo 4 counters, common preload and clear inputs
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n411 MC74419]
|-
| 74S419
| 1
| FIFO RAM controller
|
|
| 40
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n727 74S419]
|- {{anchor|74420}}
| 74x420
| 1
| 32-bit check bit / syndrome bit generator
|
| 三态逻辑
| 48
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n421 74F420]
|- {{anchor|74422}}
| 74x422
| 1
| retriggerable monostable multivibrators, two inputs
|
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls423 SN74LS422]
|- {{anchor|74423}}
| 74x423
| 2
| 2个 retriggerable monostable multivibrator
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls423 SN74LS423]
|- {{anchor|74424}}
| 74x424
| 1
| [[two-phase clock]] generator/driver for [[Intel 8080]] (equivalent to Intel 8224)
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n505 SN74LS424]
|- {{anchor|74425}}
| 74x425
| 4
| 4个 bus buffers, active low enables
|
| 三态逻辑
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1139 SN74425]
|- {{anchor|74426}}
| 74x426
| 4
| 4个 bus buffers, active high enables
|
| 三态逻辑
| 14
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1139 SN74426]
|- {{anchor|74428}}
| 74x428
| 1
| system controller for [[Intel 8080]]A (equivalent to Intel 8228)
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n253 SN74S428]
|- {{anchor|74429}}
| 74x429
| 1
| FIFO RAM controller
|
| 三态逻辑
| 28
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0037196.pdf 74LS429]
|- {{anchor|74430}}
| 74x430
| 1
| cyclic redundancy checker/corrector
|
|
| 28
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_20099339/page/n309 74F430]
|- {{anchor|74432}}
| 74x432
| 1
| 8-bit multi-mode buffered latch
|
| 三态逻辑
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n425 74F432]
|- {{anchor|74433}}
| 74x433
| 1
| 256-bit FIFO memory (64x4)
|
| 三态逻辑
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n431 74F433]
|- {{anchor|74436}}
| 74x436
| 1
| line driver/memory driver circuits - MOS memory interface, damping output resistor
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1143 SN74S436]
|- {{anchor|74437}}
| 74x437
| 1
| line driver/memory driver circuits - MOS memory interface
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1143 SN74S437]
|- {{anchor|74438}}
| 74x438
| 1
| system controller for [[Intel 8080]]A (equivalent to Intel 8238)
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n253 SN74S438]
|- {{anchor|74440}}
| 74x440
| 4
| 4个 tridirectional bus transceiver, non-inverting outputs
|
| open-collector
| 20
| [https://web.archive.org/web/20070102044619/http://focus.ti.com/lit/ds/symlink/sn74ls442.pdf SN74LS440]
|- {{anchor|74441}}
| 74x441
| 4
| 4个 tridirectional bus transceiver, inverting outputs
|
| open-collector
| 20
| [https://web.archive.org/web/20070102044619/http://focus.ti.com/lit/ds/symlink/sn74ls442.pdf SN74LS441]
|- {{anchor|74442}}
| 74x442
| 4
| 4个 tridirectional bus transceiver, non-inverting outputs
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20070102044619/http://focus.ti.com/lit/ds/symlink/sn74ls442.pdf SN74LS442]
|- {{anchor|74443}}
| 74x443
| 4
| 4个 tridirectional bus transceiver, inverting outputs
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1147 SN74LS443]
|- {{anchor|74444}}
| 74x444
| 4
| 4个 tridirectional bus transceiver, inverting and non-inverting outputs
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20070102044619/http://focus.ti.com/lit/ds/symlink/sn74ls442.pdf SN74LS444]
|- {{anchor|74445}}
| 74x445
| 1
| BCD to decimal decoders/drivers
|
| driver 80&nbsp;mA
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1153 SN74LS445]
|- {{anchor|74446}}
| 74x446
| 4
| 4个 bus transceivers, direction controls, inverting outputs
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1155 SN74LS446]
|- {{anchor|74447}}
| 74x447
| 1
| BCD to 7-segment decoders/drivers, low voltage version of 74247
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1159 SN74LS447]
|- {{anchor|74448}}
| 74x448
| 4
| 4个 tridirectional bus transceiver, inverting and non-inverting outputs
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1147 SN74LS448]
|- {{anchor|74449}}
| 74x449
| 4
| 4个 bus transceivers, direction controls, non-inverting outputs
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1155 SN74LS449]
|- {{anchor|74450}}
| 74450
| 1
| counter, latch, 7-segment decoder
| {{Unknown|{{?}}}}
| open-collector
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n419 MC74450]
|-
| 74S450
| 1
| 8192-bit PROM (1024x8) with power-down
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S450]
|-
| 74LS450
| 1
| 16-to-1 multiplexer, complementary outputs
|
|
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n201 SN74LS450]
|- {{anchor|74451}}
| 74S451
| 1
| 8192-bit PROM (1024x8) with power-down
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S451]
|-
| 74LS451
| 2
| 2个 8-to-1 multiplexer
|
|
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n205 SN74LS451]
|- {{anchor|74452}}
| 74x452
| 2
| 2个 decade counter, synchronous
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n419 MC74452]
|- {{anchor|74453}}
| 74453
| 2
| 2个 binary counter, synchronous
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n421 MC74453]
|-
| 74LS453
| 4
| 4个 4-to-1 multiplexer
|
|
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n209 SN74LS453]
|- {{anchor|74454}}
| 74x454
| 2
| 2个 decade up/down counter, synchronous, preset input
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 24
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n421 MC74454]
|- {{anchor|74455}}
| 74455
| 2
| 2个 binary up/down counter, synchronous, preset input
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 24
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n421 MC74455]
|-
| 74F455
| 1
| 8个 buffer / line driver with parity, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n505 74F455]
|- {{anchor|74456}}
| 74456
| 1
| 4-bit NBCD full adder
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n421 MC74456]
|-
| 74F456
| 1
| 8个 buffer / line driver with parity, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n505 74F456]
|- {{anchor|74458}}
| 74x458
| 1
| nines complement / zero element
| {{Unknown|{{?}}}}
| {{Unknown|{{?}}}}
| 14
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n423 MC74458]
|- {{anchor|74460}}
| 74460
| 1
| 4-bit bus transfer switch
| {{Unknown|{{?}}}}
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_motoroladauctorDataLibraryVol8Chips_17508458/page/n423 MC74460]
|-
| 74LS460
| 1
| 10-bit comparator
|
|
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n219 SN74LS460]
|- {{anchor|74461}}
| 74x461
| 1
| 8-bit presettable binary counter
|
| 三态逻辑
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n185 SN74LS461]
|- {{anchor|74462}}
| 74x462
| 1
| fiber-optic data-link transmitter
|
| open-collector 100&nbsp;mA and standard
| 20
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00215108.pdf SN74LS462]
|- {{anchor|74463}}
| 74x463
| 1
| fiber-optic data-link receiver
| analog
|
| 20
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00215108.pdf SN74LS463]
|- {{anchor|74465}}
| 74x465
| 8
| 8个 buffer, non-inverting outputs
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS465]
|- {{anchor|74466}}
| 74x466
| 8
| 8个 buffers, inverting outputs
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS466]
|- {{anchor|74467}}
| 74x467
| 8
| 8个 buffers, non-inverting outputs
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS467]
|- {{anchor|74468}}
| 74x468
| 8
| 8个 buffers, inverting outputs
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20070101063029/http://focus.ti.com/lit/ds/symlink/sn74ls465.pdf SN74LS468]
|- {{anchor|74469}}
| 74x469
| 1
| 8-bit synchronous up/down counter, parallel load and hold capability
|
| 三态逻辑
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n191 SN74LS469]
|- {{anchor|74470}}
| 74x470
| 1
| 2048-bit [[programmable read-only memory|PROM]] (256x8)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S470]
|- {{anchor|74471}}
| 74x471
| 1
| 2048-bit [[programmable read-only memory|PROM]] (256x8)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S471]
|- {{anchor|74472}}
| 74x472
| 1
| 4096-bit [[programmable read-only memory|PROM]] (512x8)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S472]
|- {{anchor|74473}}
| 74x473
| 1
| 4096-bit [[programmable read-only memory|PROM]] (512x8)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S473]
|- {{anchor|74474}}
| 74x474
| 1
| 4096-bit [[programmable read-only memory|PROM]] (512x8)
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S474]
|- {{anchor|74475}}
| 74x475
| 1
| 4096-bit [[programmable read-only memory|PROM]] (512x8)
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S475]
|- {{anchor|74476}}
| 74x476
| 1
| 4096-bit [[programmable read-only memory|PROM]] (1024x4)
|
| 三态逻辑
| 18
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S476]
|- {{anchor|74477}}
| 74x477
| 1
| 4096-bit [[programmable read-only memory|PROM]] (1024x4)
|
| open-collector
| 18
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S477]
|- {{anchor|74478}}
| 74x478
| 1
| 8192-bit [[programmable read-only memory|PROM]] (1024x8)
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S478]
|- {{anchor|74479}}
| 74x479
| 1
| 8192-bit [[programmable read-only memory|PROM]] (1024x8)
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n177 SN74S479]
|- {{anchor|74480}}
| 74x480
| 1
| 1个 burst error recovery circuit
|
|
| 24
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n727 SN74S480]
|- {{anchor|74481}}
| 74x481
| 1
| 4-bit [[slice cascadable processor]] elements
|
|
| (48)
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n15 SN74S481]
|- {{anchor|74482}}
| 74x482
| 1
| 4-bit [[bit-slicing|slice]] expandable control elements
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n259 SN74S482]
|- {{anchor|74484}}
| 74x484
| 1
| BCD-to-binary converter
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBook1986_14886851/page/n379 SN74S484A]
|- {{anchor|74485}}
| 74x485
| 1
| binary-to-BCD converter
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBook1986_14886851/page/n379 SN74S485A]
|- {{anchor|74488}}
| 74x488
| 1
| [[IEEE-488]] bus interface
|
|
| 48
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n261 74ACT488]
|- {{anchor|74490}}
| 74x490
| 2
| 2个 decade counter
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1167 SN74490]
|- {{anchor|74491}}
| 74x491
| 1
| 10-bit binary up/down counter, limited preset
|
| 三态逻辑
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n197 SN74LS491]
|- {{anchor|74498}}
| 74x498
| 1
| 8-bit bidirectional shift register, parallel inputs
|
| 三态逻辑
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n189 SN74LS498]
|-
! {{TOC tab|Part number|74x500 – 74x599}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74500}}
| 74x500
| 1
| 6-bit flash analog-to-digital converter (ADC)
| analog
|
| 24
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n409 74F500]
|- {{anchor|74502}}
| 74x502
| 1
| 8-bit successive approximation register
|
|
| 16
| [https://archive.org/details/bitsavers_fairchilddldTTLDataBook_39509923/page/n497 74LS502]
|- {{anchor|74503}}
| 74x503
| 1
| 8-bit successive approximation register with expansion control
|
|
| 16
| [https://archive.org/details/bitsavers_fairchilddldTTLDataBook_39509923/page/n501 74LS503]
|- {{anchor|74504}}
| 74x504
| 1
| 12-bit successive approximation register with expansion control
|
|
| 24
| [https://archive.org/details/bitsavers_fairchilddldTTLDataBook_39509923/page/n505 74LS504]
|- {{anchor|74505}}
| 74x505
| 1
| 8-bit [[successive approximation ADC]]
| analog
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n413 74F505]
|- {{anchor|74508}}
| 74x508
| 1
| 8-bit multiplier/divider
|
|
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n289 SN74S508]
|- {{anchor|74515}}
| 74x515
| 1
| programmable mapping decoder (2-to-4 line decoder with 9 programmable enable inputs)
|
|
| 20
| 74HCT515<ref name=hcmostb>{{cite book |title=HCMOS-Taschenbuch |trans-title=HCMOS Pocket Reference,|language=de |publisher=mitp-Verlag |place=Bonn |date=2003 |isbn=3-8266-1314-7}}</ref>{{rp|310}}
|- {{anchor|74516}}
| 74x516
| 1
| 16-bit multiplier/divider
|
|
| 24
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n365 SN74S516]
|- {{anchor|74518}}
| 74x518
| 1
| 8-bit comparator
| 20&nbsp;kΩ pull-up
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn54als520 SN74ALS518]
|- {{anchor|74519}}
| 74x519
| 1
| 8-bit comparator
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n365 SN74ALS519]
|- {{anchor|74520}}
| 74x520
| 1
| 8-bit comparator, inverting output
| 20&nbsp;kΩ pull-up
|
| 20
| [http://www.ti.com/lit/gpn/sn54als520 SN74ALS520]
|- {{anchor|74521}}
| 74x521
| 1
| 8-bit comparator, inverting output
|
|
| 20
| [http://www.ti.com/lit/gpn/sn54als520 SN74ALS521]
|- {{anchor|74522}}
| 74x522
| 1
| 8-bit comparator, inverting output
| 20&nbsp;kΩ pull-up
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n365 SN74ALS522]
|- {{anchor|74524}}
| 74x524
| 1
| 8-bit registered comparator
|
| open-collector
| 20
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n449 74F524]
|- {{anchor|74525}}
| 74x525
| 1
| 16-bit programmable counter
|
|
| 28
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n457 74F525]
|- {{anchor|74526}}
| 74x526
| 1
| fuse programmable identity comparator, 16-bit
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n371 SN74ALS526]
|- {{anchor|74527}}
| 74x527
| 1
| fuse programmable identity comparator, 8-bit + 4-bit conventional Identity comparator
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n371 SN74ALS527]
|- {{anchor|74528}}
| 74x528
| 1
| fuse programmable Identity comparator, 12-bit
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n371 SN74ALS528]
|- {{anchor|74531}}
| 74x531
| 8
| 8个 transparent latch
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n329 SN74S531]
|- {{anchor|74532}}
| 74x532
| 8
| 8个 register
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n329 SN74S532]
|- {{anchor|74533}}
| 74x533
| 1
| 8个 transparent latch, inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/cd74hct563 CD74HC533]
|- {{anchor|74534}}
| 74x534
| 1
| 8个 register, inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/cd74hc564 CD74HC534]
|- {{anchor|74535}}
| 74x535
| 1
| 8个 transparent latch, inverting outputs
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n331 SN74S535]
|- {{anchor|74536}}
| 74x536
| 1
| 8个 register, inverting outputs
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n331 SN74S536]
|- {{anchor|74537}}
| 74x537
| 1
| BCD to decimal decoder
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n247 MC74F537]
|- {{anchor|74538}}
| 74x538
| 1
| 3-to-8 line decoder/demultiplexer
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n389 SN74ALS538]
|- {{anchor|74539}}
| 74x539
| 2
| 2个 2-to-4 line decoder/demultiplexer
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n393 SN74ALS539]
|- {{anchor|74540}}
| 74x540
| 1
| 8个 非门
| Schmitt trigger
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls540 SN74LS540]
|- {{anchor|74541}}
| 74x541
| 1
| 8个 buffer gate
| Schmitt trigger
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54ls540 SN74LS541]
|- {{anchor|74543}}
| 74x543
| 1
| 8个 registered transceiver, non-inverting
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74f543 SN74F543]
|- {{anchor|74544}}
| 74x544
| 1
| 8个 registered transceiver, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n261 MC74F544]
|- {{anchor|74545}}
| 74x545
| 1
| 8个 bidirectional transceiver, non-inverting
|
| 三态逻辑
| 20
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n497 74F545]
|- {{anchor|74546}}
| 74x546
| 1
| 8-bit bidirectional registered transceiver, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS546]
|- {{anchor|74547}}
| 74LS547
| 1
| 8-bit bidirectional latched transceiver, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS547]
|-
| 74F547
| 1
| 3-to-8 line decoder/demultiplexer with address latches and acknowledge output
|
|
| 20
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n501 74F547]
|- {{anchor|74548}}
| 74LS548
| 1
| 8-bit two-stage pipelined register
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n637 SN74LS548]
|-
| 74F548
| 1
| 3-to-8 line decoder/demultiplexer with acknowledge output
|
|
| 20
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n505 74F548]
|- {{anchor|74549}}
| 74x549
| 1
| 8-bit two-stage pipelined latch
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n637 SN74LS549]
|- {{anchor|74550}}
| 74x550
| 1
| 8个 registered transceiver with status flags, non-inverting
|
| 三态逻辑
| 28
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n509 74F550]
|- {{anchor|74551}}
| 74x551
| 1
| 8个 registered transceiver with status flags, inverting
|
| 三态逻辑
| 28
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n509 74F551]
|- {{anchor|74552}}
| 74x552
| 1
| 8个 registered transceiver with parity and flags
|
| 三态逻辑
| 28
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n515 74F552]
|- {{anchor|74556}}
| 74x556
| 1
| 16x16-bit multiplier slice
|
| 三态逻辑
| (84)
| [https://archive.org/details/bitsavers_mmidataBook7ed_126879625/page/n567 74S556]
|- {{anchor|74557}}
| 74x557
| 1
| 8-bit by 8-bit multiplier
|
| 三态逻辑
| 40
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n381 SN74S557]
|- {{anchor|74558}}
| 74x558
| 1
| 8-bit by 8-bit multiplier
|
| 三态逻辑
| 40
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n381 SN74S558]
|- {{anchor|74559}}
| 74x559
| 1
| 8-bit expandable two's complement multiplier/divider
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_20099339/page/n311 74F559]
|- {{anchor|74560}}
| 74x560
| 1
| 4-bit decade counter
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n401 SN74ALS560A]
|- {{anchor|74561}}
| 74x561
| 1
| 4-bit binary counter
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20170305192612/http://www.ti.com/lit/ds/symlink/sn74als561a.pdf SN74ALS561A]
|- {{anchor|74563}}
| 74x563
| 1
| 8-bit D-type transparent latch, inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54als563b SN74ALS563B]
|- {{anchor|74564}}
| 74x564
| 1
| 8-bit D-type edge-triggered register, inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn54als564b SN74ALS564B]
|- {{anchor|74566}}
| 74x566
| 1
| 8-bit bidirectional registered transceiver, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS566]
|- {{anchor|74567}}
| 74x567
| 1
| 8-bit bidirectional latched transceiver, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_mmidataBook6ed_79579213/page/n589 SN74LS567]
|- {{anchor|74568}}
| 74x568
| 1
| decade up/down counter
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als569a SN74ALS568A]
|- {{anchor|74569}}
| 74x569
| 1
| binary up/down counter
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als569a SN74ALS569A]
|- {{anchor|74570}}
| 74x570
| 1
| 2048-bit PROM (512x4)
|
| open-collector
| 16
| [https://archive.org/details/bitsavers_nationaldataBook_16727669/page/n315 DM74S570]
|- {{anchor|74571}}
| 74x571
| 1
| 2048-bit PROM (512x4)
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_nationaldataBook_16727669/page/n315 DM74S571]
|- {{anchor|74572}}
| 74x572
| 1
| 4096-bit PROM (1024x4)
|
| open-collector
| 18
| [https://archive.org/details/bitsavers_nationaldataBook_16727669/page/n317 DM74S572]
|- {{anchor|74573}}
| 74x573
| 1
| 8个 D-type transparent latch
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als573c SN74ALS573C]
|- {{anchor|74574}}
| 74x574
| 1
| 8个 D-type edge-triggered flip-flop
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/ds/symlink/sn74hc574.pdf SN74HC574]
|- {{anchor|74575}}
| 74x575
| 1
| 8个 D-type edge-triggered flip-flop, synchronous clear
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als575a SN74ALS575A]
|- {{anchor|74576}}
| 74x576
| 1
| 8个 D-type edge-triggered flip-flop, inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74as576 SN74ALS576B]
|- {{anchor|74577}}
| 74x577
| 1
| 8个 D-type edge-triggered flip-flop, synchronous clear, inverting outputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74as576 SN74ALS577A]
|- {{anchor|74579}}
| 74x579
| 1
| 8-bit bidirectional binary counter
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n273 MC74F579]
|- {{anchor|74580}}
| 74x580
| 1
| 8个 D-type transparent latch, inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als580b SN74ALS580B]
|- {{anchor|74582}}
| 74x582
| 1
| 4-bit BCD arithmetic logic unit
|
|
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n551 74F582]
|- {{anchor|74583}}
| 74x583
| 1
| 4-bit BCD adder
|
|
| 16
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n555 74F583]
|- {{anchor|74588}}
| 74x588
| 1
| 8个 bidirectional transceiver with [[IEEE-488]] termination resistors
|
| 三态逻辑
| 20
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n559 74F588]
|- {{anchor|74589}}
| 74x589
| 1
| 8-bit shift register, input latch
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1181 SN74LS589]
|- {{anchor|74590}}
| 74x590
| 1
| 8-bit binary counter, output registers
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn74ls590 SN74LS590]
|- {{anchor|74591}}
| 74x591
| 1
| 8-bit binary counter, output registers
|
| open-collector
| 16
| [http://www.ti.com/lit/gpn/sn74ls590 SN74LS591]
|- {{anchor|74592}}
| 74x592
| 1
| 8-bit binary counter, input registers
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls592 SN74LS592]
|- {{anchor|74593}}
| 74x593
| 1
| 8-bit binary counter, input registers
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls592 SN74LS593]
|- {{anchor|74594}}
| 74x594
| 1
| 8-bit shift registers, Serial-In, Parallel-Out, output latches
|
| buffered
| 16
| [http://www.ti.com/lit/gpn/sn74ls594 SN74LS594]
|- {{anchor|74595}}
| 74x595
| 1
| 8-bit shift registers, Serial-In, Parallel-Out, output latches, output enable
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn74ls595 SN74LS595]
|- {{anchor|74596}}
| 74x596
| 1
| 8-bit shift registers, Serial-In, Parallel-Out, output latches, output enable
|
| open-collector
| 16
| [http://www.ti.com/lit/gpn/sn74ls595 SN74LS596]
|- {{anchor|74597}}
| 74x597
| 1
| 8-bit shift registers, Parallel-In, Serial-Out, input latches
|
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls597 SN74LS597]
|- {{anchor|74598}}
| 74x598
| 1
| 8-bit shift register, Selectable Parallel-In/Out input latches
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls597 SN74LS598]
|- {{anchor|74599}}
| 74x599
| 1
| 8-bit shift registers, Serial-In, Parallel-Out, output latches
|
| open-collector
| 16
| [http://www.ti.com/lit/gpn/sn74ls594 SN74LS599]
|-
! {{TOC tab|Part number|74x600 – 74x699}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74600}}
| 74x600
| 1
| dynamic memory refresh controller, transparent and burst modes, for 4K or 16K dRAM
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS600A]
|- {{anchor|74601}}
| 74x601
| 1
| dynamic memory refresh controller, transparent and burst modes, for 64K dRAM
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS601A]
|- {{anchor|74602}}
| 74x602
| 1
| dynamic memory refresh controller, cycle steal and burst modes, for 4K or 16K dRAM
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS602A]
|- {{anchor|74603}}
| 74x603
| 1
| dynamic memory refresh controller, cycle steal and burst modes, for 64K dRAM
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1217 SN74LS603A]
|- {{anchor|74604}}
| 74x604
| 1
| 8个 2输入 multiplexer, latch, high-speed
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1225 SN74LS604]
|- {{anchor|74605}}
| 74x605
| 1
| 8个 2输入 multiplexer, latch, high-speed
|
| open-collector
| 28
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1225 SN74LS605]
|- {{anchor|74606}}
| 74x606
| 1
| 8个 2输入 multiplexer, latch, glitch-free
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1225 SN74LS606]
|- {{anchor|74607}}
| 74x607
| 1
| 8个 2输入 multiplexer, latch, glitch-free
|
| open-collector
| 28
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1225 SN74LS607]
|- {{anchor|74608}}
| 74x608
| 1
| memory cycle controller
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1231 SN74LS608]
|- {{anchor|74610}}
| 74x610
| 1
| memory mapper, latched
|
| 三态逻辑
| 40
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1237 SN74LS610]
|- {{anchor|74611}}
| 74x611
| 1
| memory mapper, latched
|
| open-collector
| 40
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1237 SN74LS611]
|- {{anchor|74612}}
| 74x612
| 1
| memory mapper
|
| 三态逻辑
| 40
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1237 SN74LS612]
|- {{anchor|74613}}
| 74x613
| 1
| memory mapper
|
| open-collector
| 40
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1237 SN74LS613]
|- {{anchor|74614}}
| 74x614
| 1
| 8个 bus transceiver and register, inverting
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n495 SN74ALS614]
|- {{anchor|74615}}
| 74x615
| 1
| 8个 bus transceiver and register, non-inverting
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n495 SN74ALS615]
|- {{anchor|74616}}
| 74x616
| 1
| 16-bit parallel error detection and correction
|
| 三态逻辑
| 40
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n101 SN74ALS616]
|- {{anchor|74617}}
| 74x617
| 1
| 16-bit parallel error detection and correction
|
| open-collector
| 40
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n101 SN74ALS617]
|- {{anchor|74620}}
| 74x620
| 1
| 8个 bus transceiver, inverting
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls623 SN74LS620]
|- {{anchor|74621}}
| 74x621
| 1
| 8个 bus transceiver, non-inverting
|
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn74ls623 SN74LS621]
|- {{anchor|74622}}
| 74x622
| 1
| 8个 bus transceiver, inverting
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1247 SN74LS622]
|- {{anchor|74623}}
| 74x623
| 1
| 8个 bus transceiver, non-inverting
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls623 SN74LS623]
|- {{anchor|74624}}
| 74x624
| 1
| [[voltage-controlled oscillator]], enable control, range control, two-phase outputs
| analog
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls624 SN74LS624]
|- {{anchor|74625}}
| 74x625
| 2
| 2个 [[voltage-controlled oscillator]], two-phase outputs
| analog
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls624 SN74LS625]
|- {{anchor|74626}}
| 74x626
| 2
| 2个 [[voltage-controlled oscillator]], enable control, two-phase outputs
| analog
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls624 SN74LS626]
|- {{anchor|74627}}
| 74x627
| 2
| 2个 [[voltage-controlled oscillator]]
| analog
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls624 SN74LS627]
|- {{anchor|74628}}
| 74x628
| 1
| [[voltage-controlled oscillator]], enable control, range control,<br/> external temperature compensation, two-phase outputs
| analog
|
| 14
| [http://www.ti.com/lit/gpn/sn74ls624 SN74LS628]
|- {{anchor|74629}}
| 74x629
| 2
| 2个 [[voltage-controlled oscillator]], enable control, range control
| analog
|
| 16
| [http://www.ti.com/lit/gpn/sn74ls624 SN74LS629]
|- {{anchor|74630}}
| 74x630
| 1
| 16-bit error detection and correction (EDAC)
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1263 SN74LS630]
|- {{anchor|74631}}
| 74x631
| 1
| 16-bit error detection and correction
|
| open-collector
| 28
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1263 SN74LS631]
|- {{anchor|74632}}
| 74x632
| 1
| 32-bit parallel error detection and correction, byte-write
|
| 三态逻辑
| 52
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n457 SN74ALS632]
|- {{anchor|74633}}
| 74x633
| 1
| 32-bit parallel error detection and correction, byte-write
|
| open-collector
| 52
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n457 SN74ALS633]
|- {{anchor|74634}}
| 74x634
| 1
| 32-bit parallel error detection and correction
|
| 三态逻辑
| 48
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n457 SN74ALS634]
|- {{anchor|74635}}
| 74x635
| 1
| 32-bit parallel error detection and correction
|
| open-collector
| 48
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n457 SN74ALS635]
|- {{anchor|74636}}
| 74x636
| 1
| 8-bit parallel error detection and correction
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1271 SN74LS636]
|- {{anchor|74637}}
| 74x637
| 1
| 8-bit parallel error detection and correction
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1271 SN74LS637]
|- {{anchor|74638}}
| 74x638
| 1
| 8个 bus transceiver, inverting outputs
|
| 三态逻辑 and open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1279 SN74LS638]
|- {{anchor|74639}}
| 74x639
| 1
| 8个 bus transceiver, non-inverting outputs
|
| 三态逻辑 and open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1279 SN74LS639]
|- {{anchor|74640}}
| 74x640
| 1
| 8个 bus transceiver, inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls640 SN74LS640]
|- {{anchor|74641}}
| 74x641
| 1
| 8个 bus transceiver, non-inverting outputs
|
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn74ls640 SN74LS641]
|- {{anchor|74642}}
| 74x642
| 1
| 8个 bus transceiver, inverting outputs
|
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn74ls640 SN74LS642]
|- {{anchor|74643}}
| 74x643
| 1
| 8个 bus transceiver, mix of inverting and non-inverting outputs
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1283 SN74LS643]
|- {{anchor|74644}}
| 74x644
| 1
| 8个 bus transceiver, mix of inverting and non-inverting outputs
|
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn74ls640 SN74LS644]
|- {{anchor|74645}}
| 74x645
| 1
| 8个 bus transceiver, non-inverting outputs
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls640 SN74LS645]
|- {{anchor|74646}}
| 74x646
| 1
| 8个 bus transceiver/latch/multiplexer, non-inverting outputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn54als648 SN74ALS646A]
|- {{anchor|74647}}
| 74x647
| 1
| 8个 bus transceiver/latch/multiplexer, non-inverting outputs
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1291 SN74LS647]
|- {{anchor|74648}}
| 74x648
| 1
| 8个 bus transceiver/latch/multiplexer, inverting outputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn54als648 SN74ALS648A]
|- {{anchor|74649}}
| 74x649
| 1
| 8个 bus transceiver/latch/multiplexer, inverting outputs
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1291 SN74LS649]
|- {{anchor|74651}}
| 74x651
| 1
| 8个 bus transceiver/register, inverting outputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als654 SN74ALS651A]
|- {{anchor|74652}}
| 74x652
| 1
| 8个 bus transceiver/register, non-inverting outputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als654 SN74ALS652A]
|- {{anchor|74653}}
| 74x653
| 1
| 8个 bus transceiver/register, inverting outputs
|
| 三态逻辑 and open-collector
| 24
| [http://www.ti.com/lit/gpn/sn74als654 SN74ALS653]
|- {{anchor|74654}}
| 74x654
| 1
| 8个 bus transceiver/register, non-inverting outputs
|
| 三态逻辑 and open-collector
| 24
| [http://www.ti.com/lit/gpn/sn74als654 SN74ALS654]
|- {{anchor|74655}}
| 74x655
| 1
| 8个 buffer / line driver with parity, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n553 74F655]
|- {{anchor|74656}}
| 74x656
| 1
| 8个 buffer / line driver with parity, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n553 74F656]
|- {{anchor|74657}}
| 74x657
| 1
| 8个 bidirectional transceiver with 8-bit parity generator/checker
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74f657 SN74F657]
|- {{anchor|74658}}
| 74x658
| 1
| 8个 bus transceiver, parity, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n395 SN74HC658]
|- {{anchor|74659}}
| 74x659
| 1
| 8个 bus transceiver, parity, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n395 SN74HC659]
|- {{anchor|74664}}
| 74x664
| 1
| 8个 bus transceiver, parity, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n409 SN74HC664]
|- {{anchor|74665}}
| 74x665
| 1
| 8个 bus transceiver, parity, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n409 SN74HC665]
|- {{anchor|74666}}
| 74x666
| 1
| 8-bit D-type transparent read-back latch, non-inverting
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als666 SN74ALS666]
|- {{anchor|74667}}
| 74x667
| 1
| 8-bit D-type transparent read-back latch, inverting
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als666 SN74ALS667]
|- {{anchor|74668}}
| 74x668
| 1
| synchronous 4-bit decade up/down counter
|
|
| 16
| [https://web.archive.org/web/20060602131759/http://focus.ti.com/lit/ds/symlink/sn74ls669.pdf SN74LS668]
|- {{anchor|74669}}
| 74x669
| 1
| synchronous 4-bit binary up/down counter
|
|
| 16
| [https://web.archive.org/web/20060602131759/http://focus.ti.com/lit/ds/symlink/sn74ls669.pdf SN74LS669]
|- {{anchor|74670}}
| 74x670
| 1
| 16-bit register file (4x4)
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/sn54ls670 SN74LS670]
|- {{anchor|74671}}
| 74x671
| 1
| 4-bit bidirectional shift register/latch/multiplexer, direct clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1327 SN74LS671]
|- {{anchor|74672}}
| 74x672
| 1
| 4-bit bidirectional shift register/latch/multiplexer, synchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1327 SN74LS672]
|- {{anchor|74673}}
| 74x673
| 1
| 16-bit serial-in, serial/parallel-out shift register, output storage registers
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74ls673 SN74LS673]
|- {{anchor|74674}}
| 74x674
| 1
| 16-bit parallel-in, serial-out shift register
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74ls673 SN74LS674]
|- {{anchor|74675}}
| 74x675
| 1
| 16-bit serial-in, serial/parallel-out shift register
|
|
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n607 74F675A]
|- {{anchor|74676}}
| 74x676
| 1
| 16-bit serial/parallel-in, serial-out shift register
|
|
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n611 74F676]
|- {{anchor|74677}}
| 74x677
| 1
| 16-bit address [[comparator]], enable
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n507 SN74ALS677]
|- {{anchor|74678}}
| 74x678
| 1
| 16-bit address comparator, latch
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n507 SN74ALS678]
|- {{anchor|74679}}
| 74x679
| 1
| 12-bit address comparator, latch
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n513 SN74ALS679]
|- {{anchor|74680}}
| 74x680
| 1
| 12-bit address comparator, enable
|
|
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n513 SN74ALS680]
|- {{anchor|74681}}
| 74x681
| 1
| 4-bit parallel binary accumulator
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1339 SN74LS681]
|- {{anchor|74682}}
| 74x682
| 1
| 8-bit [[digital comparator|magnitude comparator]], P>Q output
| 20&nbsp;kΩ pull-up
|
| 20
| [https://web.archive.org/web/20160531200122/http://www.ti.com/lit/ds/symlink/sn74ls682.pdf SN74LS682]
|- {{anchor|74683}}
| 74x683
| 1
| 8-bit magnitude comparator, P>Q output
| 20&nbsp;kΩ pull-up
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1345 SN74LS683]
|- {{anchor|74684}}
| 74x684
| 1
| 8-bit magnitude comparator, P>Q output
|
|
| 20
| [https://web.archive.org/web/20160531200122/http://www.ti.com/lit/ds/symlink/sn74ls682.pdf SN74LS684]
|- {{anchor|74685}}
| 74x685
| 1
| 8-bit magnitude comparator, P>Q output
|
| open-collector
| 20
| [https://web.archive.org/web/20160531200122/http://www.ti.com/lit/ds/symlink/sn74ls682.pdf SN74LS685]
|- {{anchor|74686}}
| 74x686
| 1
| 8-bit magnitude comparator, P>Q output, enable
|
|
| 24
| [https://web.archive.org/web/20160531200122/http://www.ti.com/lit/ds/symlink/sn74ls682.pdf SN74LS686]
|- {{anchor|74687}}
| 74x687
| 1
| 8-bit magnitude comparator, P>Q output, enable
|
| open-collector
| 24
| [https://web.archive.org/web/20160531200122/http://www.ti.com/lit/ds/symlink/sn74ls682.pdf SN74LS687]
|- {{anchor|74688}}
| 74x688
| 1
| 8-bit magnitude comparator, enable
|
|
| 20
| [https://web.archive.org/web/20160531200122/http://www.ti.com/lit/ds/symlink/sn74ls682.pdf SN74LS688]
|- {{anchor|74689}}
| 74x689
| 1
| 8-bit magnitude comparator, enable
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1345 SN74LS689]
|- {{anchor|74690}}
| 74x690
| 1
| 4-bit decimal counter/latch/multiplexer, asynchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS690]
|- {{anchor|74691}}
| 74x691
| 1
| 4-bit binary counter/latch/multiplexer, asynchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS691]
|- {{anchor|74692}}
| 74x692
| 1
| 4-bit decimal counter/latch/multiplexer, synchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS692]
|- {{anchor|74693}}
| 74x693
| 1
| 4-bit binary counter/latch/multiplexer, synchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1353 SN74LS693]
|- {{anchor|74694}}
| 74x694
| 1
| 4-bit decimal counter/latch/multiplexer,  synchronous and asynchronous clears
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_icMaster19_159569496/page/n619 SN74ALS694]
|- {{anchor|74695}}
| 74x695
| 1
| 4-bit binary counter/latch/multiplexer, synchronous and asynchronous clears
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_icMaster19_159569496/page/n619 SN74ALS695]
|- {{anchor|74696}}
| 74x696
| 1
| 4-bit decimal counter/register/multiplexer, asynchronous clear
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls697 SN74LS696]
|- {{anchor|74697}}
| 74x697
| 1
| 4-bit binary counter/register/multiplexer, asynchronous clear
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls697 SN74LS697]
|- {{anchor|74698}}
| 74x698
| 1
| 4-bit decimal counter/register/multiplexer, synchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1365 SN74LS698]
|- {{anchor|74699}}
| 74x699
| 1
| 4-bit binary counter/register/multiplexer, synchronous clear
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74ls697 SN74LS699]
|-
! {{TOC tab|Part number|74x700 – 74x799}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74700}}
| 74x700
| 1
| 8个 dRAM driver, inverting
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S700]
|- {{anchor|74701}}
| 74x701
| 1
| 8-bit register/counter/comparator
|
| 三态逻辑
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n615 74F701]
|- {{anchor|74702}}
| 74x702
| 1
| 8-bit registered read-back transceiver
|
| 三态逻辑
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n617 74F702]
|- {{anchor|74705}}
| 74x705
| 1
| arithmetic logic unit for digital signal processing applications
|
| 三态逻辑
| (84)
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n349 74ACT705]
|- {{anchor|74707}}
| 74x707
| 1
| 8-bit TTL-ECL shift register
|
|
| 20
| [https://archive.org/details/bitsavers_nationaldaFASTDatabook_31226275/page/n621 74F707]
|- {{anchor|74708}}
| 74x708
| 1
| 576-bit FIFO memory (64x9)
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n361 74ACT708]
|- {{anchor|74710}}
| 74x710
| 1
| 8-bit single-supply TTL-ECL shift register
|
|
| 20
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n621 74F710]
|- {{anchor|74711}}
| 74x711
| 5
| quint 2-to-1 multiplexers
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n777 74F711]
|- {{anchor|74712}}
| 74x712
| 5
| quint 3-to-1 multiplexers
|
|
| 24
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n777 74F712]
|- {{anchor|74715}}
| 74x715
| 1
| programmable video sync generator
|
|
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-303/53948.pdf 74ACT715]
|- {{anchor|74716}}
| 74x716
| 1
| programmable decade counter
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n397 SN74LS716]
|- {{anchor|74718}}
| 74x718
| 1
| programmable binary counter
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n397 SN74LS718]
|- {{anchor|74723}}
| 74x723
| 1
| 576-bit FIFO memory (64x9)
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n379 74ACT723]
|- {{anchor|74724}}
| 74x724
| 1
| voltage-controlled multivibrator
| analog
|
| 8
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n409 SN74LS724]
|- {{anchor|74725}}
| 74x725
| 1
| 4608-bit FIFO memory (512x9)
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n395 74ACT725]
|- {{anchor|74730}}
| 74x730
| 1
| 8个 dRAM driver, inverting
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S730]
|- {{anchor|74731}}
| 74x731
| 1
| 8个 dRAM driver, non-inverting
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S731]
|- {{anchor|74732}}
| 74x732
| 1
| 4-bit 3-bus multiplexer, inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n789 74F732]
|- {{anchor|74733}}
| 74x733
| 1
| 4-bit 3-bus multiplexer, non-inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n789 74F733]
|- {{anchor|74734}}
| 74x734
| 1
| 8个 dRAM driver, non-inverting
|
| 三态逻辑
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n315 SN74S734]
|- {{anchor|74740}}
| 74x740
| 2
| 2个 4-bit line driver, inverting
|
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137088.pdf SN74S740]
|- {{anchor|74741}}
| 74x741
| 2
| 2个 4-bit line driver, non-inverting, complementary enable inputs
|
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137088.pdf SN74S741]
|- {{anchor|74742}}
| 74x742
| 1
| 8个 line driver, inverting
|
| open-collector
| 20
| SN74ALS742<ref name=ttltb3>{{cite book |title=TTL-Taschenbuch, Teil 3 |trans-title=TTL Pocket Reference, Part 3 |language=de |publisher=mitp-Verlag |place=Bonn |date=2002 |isbn=3-8266-0802-X}}</ref>{{rp|at=3-122}} <ref name=catalogo>{{cite web |title=Catálogo de Componentes |trans-title=Components Catalog |language=es |url=http://www.reniemarquet.com/kicad/libs/o_ttl.pdf |date=2006-01-20 |access-date=2022-01-17}}</ref>{{rp|page=25}}
|- {{anchor|74743}}
| 74x743
| 1
| 8个 line driver, non-inverting
|
| open-collector
| 20
| SN74ALS743<ref name=ttltb3/>{{rp|at=3-124}} <ref name=catalogo/>{{rp|page=25}}
|- {{anchor|74744}}
| 74x744
| 2
| 2个 4-bit line driver, non-inverting
|
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137088.pdf SN74S744]
|- {{anchor|74746}}
| 74x746
| 1
| 8个 buffer / line driver, inverting
| 20&nbsp;kΩ pull-up
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n623 SN74ALS746]
|- {{anchor|74747}}
| 74x747
| 1
| 8个 buffer / line driver, non-inverting
| 20&nbsp;kΩ pull-up
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n623 SN74ALS747]
|- {{anchor|74748}}
| 74x748
| 1
| 8 to 3-line priority encoder (glitch-less)
|
|
| 16
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n151 SN74LS748]
|- {{anchor|74756}}
| 74x756
| 1
| 8个 buffer/line driver, inverting outputs
|
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn54as756 SN74AS756]
|- {{anchor|74757}}
| 74x757
| 1
| 8个 buffer/line driver, non-inverting outputs, complementary enable inputs
|
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn54as756 SN74AS757]
|- {{anchor|74758}}
| 74x758
| 1
| quadruple bus transceivers, inverting outputs
|
| open-collector
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n527 SN74AS758]
|- {{anchor|74759}}
| 74x759
| 1
| quadruple bus transceivers, non-inverting outputs
|
| open-collector
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n527 SN74AS759]
|- {{anchor|74760}}
| 74x760
| 1
| 8个 buffer/line driver, non-inverting outputs
|
| open-collector
| 20
| [http://www.ti.com/lit/gpn/sn54as760 SN74ALS760]
|- {{anchor|74762}}
| 74x762
| 1
| 8个 buffer/line driver, inverting and non-inverting outputs
|
| open-collector
| 20
| [https://web.archive.org/web/20170224211619/http://www.ti.com/lit/ds/symlink/sn74as762.pdf SN74ALS762]
|- {{anchor|74763}}
| 74x763
| 1
| 8个 buffer/line driver, inverting outputs, complementary enable inputs
|
| open-collector
| 20
| [https://web.archive.org/web/20170224211619/http://www.ti.com/lit/ds/symlink/sn74as762.pdf SN74ALS763]
|- {{anchor|74764}}
| 74x764
| 1
| 2个-port dRAM controller
|
|
| 40
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n795 74F764]
|- {{anchor|74765}}
| 74x765
| 1
| 2个-port dRAM controller with address latch
|
|
| 40
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n795 74F765]
|- {{anchor|74776}}
| 74x776
| 1
| 8-bit latched transceiver for [[FutureBus]]
|
| 三态逻辑 and open-collector
| 28
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n453 SN74F776]
|- {{anchor|74777}}
| 74x777
| 3
| 3个 latched transceiver
|
| 三态逻辑 and open-collector
| 20
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F777_PhilipsSemiconductors.pdf 74F777]
|- {{anchor|74779}}
| 74x779
| 1
| 8-bit bidirectional binary counter
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n297 MC74F779]
|- {{anchor|74783}}
| 74x783
| 1
| synchronous address multiplexer for display systems
|
|
| 40
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n411 SN74LS783]
|- {{anchor|74784}}
| 74x784
| 1
| 8-bit serial/parallel multiplier with adder/subtractor
|
|
| 20
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n583 74F784]
|- {{anchor|74785}}
| 74x785
| 1
| synchronous address multiplexer for display systems with 256-column refresh
|
|
| 40
| [https://cdn.datasheetspdf.com/pdf-down/S/N/7/SN74LS783_MotorolaSemiconductor.pdf SN74LS785]
|- {{anchor|74786}}
| 74x786
| 1
| 4输入 asynchronous bus arbiter
|
|
| 16
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n835 74F786]
|- {{anchor|74790}}
| 74x790
| 1
| error detection and correction (EDAC)
|
| 三态逻辑
| 48
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n629 SN74ALS790]
|- {{anchor|74793}}
| 74x793
| 1
| 8-bit latch, readback
|
|
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n433 SN74LS793]
|- {{anchor|74794}}
| 74x794
| 1
| 8-bit register, readback
|
|
| 20
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1984DatabookOCR#page/n433 SN74LS794]
|- {{anchor|74795}}
| 74x795
| 1
| 8个 buffer, non-inverting, common enable
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS795]
|- {{anchor|74796}}
| 74x796
| 1
| 8个 buffer, inverting, common enable
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS796]
|- {{anchor|74797}}
| 74x797
| 1
| 8个 buffer, non-inverting, enable for 4 buffers each
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS797]
|- {{anchor|74798}}
| 74x798
| 1
| 8个 buffer, inverting, enable for 4 buffers each
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n437 SN74LS798]
|-
! {{TOC tab|Part number|74x800 – 74x899}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74800}}
| 74x800
| 3
| 3个 4输入 AND/NAND drivers
|
| driver
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n537 SN74AS800]
|- {{anchor|74802}}
| 74x802
| 3
| 3个 4输入 OR/NOR drivers
|
| driver
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n541 SN74AS802]
|- {{anchor|74803}}
| 74x803
| 4
| 4个 D flip flops with matched propagation delays
|
|
| 14
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n301 MC74F803]
|- {{anchor|74804}}
| 74x804
| 6
| 6个 2输入 NAND drivers
|
| driver
| 20
| [http://www.ti.com/lit/gpn/sn54as804b SN74ALS804A]
|- {{anchor|74805}}
| 74x805
| 6
| 6个 2输入 NOR drivers
|
| driver
| 20
| [http://www.ti.com/lit/gpn/sn54as805b SN74ALS805A]
|- {{anchor|74807}}
| 74x807
| 1
| 1-to-10 clock driver
|
| driver
| 20
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n569 IDT74FCT807]
|- {{anchor|74808}}
| 74x808
| 6
| 6个 2输入 AND drivers
|
| driver
| 20
| [http://www.ti.com/lit/gpn/sn74as808b SN74AS808B]
|- {{anchor|74810}}
| 74x810
| 4
| 4个 2输入 XNOR异或非门
|
|
| 14
| [https://web.archive.org/web/20170225141941/http://www.ti.com/lit/ds/symlink/sn74als810.pdf SN74ALS810]
|- {{anchor|74811}}
| 74x811
| 4
| 4个 2输入 XNOR异或非门
|
| open-collector
| 14
| [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n349 DM74ALS811]
|- {{anchor|74818}}
| 74x818
| 1
| 8-bit diagnostic register
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n411 74ACT818]
|- {{anchor|74819}}
| 74x819
| 1
| 8-bit diagnostic / pipeline register
|
| 三态逻辑
| 24
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/466541/TI1/SN74ALS819.html SN74ALS819]
|- {{anchor|74821}}
| 74x821
| 1
| 10-bit bus interface flip-flop
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn54as821a SN74AS821A]
|- {{anchor|74822}}
| 74x822
| 1
| 10-bit bus interface flip-flop, inverting inputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n557 SN74AS822]
|- {{anchor|74823}}
| 74x823
| 1
| 9-bit D-type flip-flops, clear and clock enable inputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn54as823a SN74AS823A]
|- {{anchor|74824}}
| 74x824
| 1
| 9-bit D-type flip-flops, clear and clock enable inputs, inverting inputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n563 SN74AS824]
|- {{anchor|74825}}
| 74x825
| 1
| 8-bit D-type flip-flop, clear and clock enable inputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn54as825a SN74AS825A]
|- {{anchor|74826}}
| 74x826
| 1
| 8-bit D-type flip-flop, clear and clock enable inputs, inverting inputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n569 SN74AS826]
|- {{anchor|74827}}
| 74x827
| 1
| 10-bit buffer, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n303 MC74F827]
|- {{anchor|74828}}
| 74x828
| 1
| 10-bit buffer, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/nd_LS_TTL_Data#page/n303 MC74F828]
|- {{anchor|74832}}
| 74x832
| 6
| 6个 2输入 OR drivers
|
| driver
| 20
| [https://web.archive.org/web/20170221112630/http://www.ti.com/lit/ds/symlink/sn74als832a.pdf SN74ALS832A]
|- {{anchor|74833}}
| 74x833
| 1
| 8-bit to 9-bit bus transceiver with parity register, non-inverting
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74abt833 SN74ABT833]
|- {{anchor|74834}}
| 74x834
| 1
| 8-bit to 9-bit bus transceiver with parity register, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_idtdataBoomanceCMOSDataBook_66222191/page/n1071 IDT74FCT834]
|- {{anchor|74835}}
| 74x835
| 1
| 8-bit shift register with 2:1 input multiplexers, one input latched, serial output
|
|
| 24
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F835_PhilipsSemiconductors.pdf 74F835]
|- {{anchor|74839}}
| 74x839
| 1
| field-programmable logic array 14x32x6
|
| 三态逻辑
| 24
| [https://archive.org/details/TexasInstruments-TI-Data-TtlDataBookVol1_1984-DL/page/n259 SN74PL839]
|- {{anchor|74840}}
| 74x840
| 1
| field-programmable logic array 14x32x6
|
| open-collector
| 24
| [https://archive.org/details/TexasInstruments-TI-Data-TtlDataBookVol1_1984-DL/page/n259 SN74PL840]
|- {{anchor|74841}}
| 74x841
| 1
| 10-bit D-type flip-flop
|
| 三态逻辑
| 24
| [https://web.archive.org/web/20170225141931/http://www.ti.com/lit/ds/symlink/sn74als841.pdf SN74ALS841]
|- {{anchor|74842}}
| 74x842
| 1
| 10-bit D-type flip-flop, inverting inputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n579 SN74ALS842]
|- {{anchor|74843}}
| 74x843
| 1
| 9-bit D flip-flops, clear and set inputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als843 SN74ALS843]
|- {{anchor|74844}}
| 74x844
| 1
| 9-bit D flip-flops, clear and set inputs, inverting inputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n587 SN74ALS844]
|- {{anchor|74845}}
| 74x845
| 1
| 8-bit D flip-flops, clear and set inputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n595 SN74ALS845]
|- {{anchor|74846}}
| 74x846
| 1
| 8-bit D flip-flops, clear and set inputs, inverting inputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n595 SN74ALS846]
|- {{anchor|74848}}
| 74x848
| 1
| 8 to 3-line priority encoder (glitch-less)
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n315 SN74LS848]
|- {{anchor|74850}}
| 74x850
| 1
| 1 of 16 data selector/multiplexer, clocked select
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n603 SN74AS850]
|- {{anchor|74851}}
| 74x851
| 1
| 1 of 16 data selector/multiplexer
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n603 SN74AS851]
|- {{anchor|74852}}
| 74x852
| 1
| 8-bit universal transceiver port controller
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n613 SN74AS852]
|- {{anchor|74853}}
| 74x853
| 1
| 8-bit to 9-bit bus transceiver with parity latch, non-inverting
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74abt853 SN74ABT853]
|- {{anchor|74854}}
| 74x854
| 1
| 8-bit to 9-bit bus transceiver with parity latch, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_idtdataBoomanceCMOSDataBook_66222191/page/n1071 IDT74FCT854]
|- {{anchor|74856}}
| 74x856
| 1
| 8-bit universal transceiver port controller
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n619 SN74AS856]
|- {{anchor|74857}}
| 74x857
| 6
| 6个 2-line to 1-line multiplexer
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn54als857 SN74ALS857]
|- {{anchor|74861}}
| 74x861
| 1
| 10-bit bus transceiver, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBook_80793740/page/n263 SN74ABT861]
|- {{anchor|74862}}
| 74x862
| 1
| 10-bit bus transceiver, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBook_80793740/page/n269 SN74ABT862]
|- {{anchor|74863}}
| 74x863
| 1
| 9-bit bus transceiver, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBook_80793740/page/n273 SN74ABT863]
|- {{anchor|74864}}
| 74x864
| 1
| 9-bit bus transceiver, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n867 74F864]
|- {{anchor|74866}}
| 74x866
| 1
| 8-bit magnitude comparator with latches
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n633 SN74AS866]
|- {{anchor|74867}}
| 74x867
| 1
| synchronous 8-bit up/down counter, asynchronous clear
|
|
| 24
| [http://www.ti.com/lit/gpn/sn74als867a SN74ALS867A]
|- {{anchor|74869}}
| 74x869
| 1
| synchronous 8-bit up/down counter, synchronous clear
|
|
| 24
| [http://www.ti.com/lit/gpn/sn74als867a SN74ALS869]
|- {{anchor|74870}}
| 74x870
| 1
| 2个 16x4 register files
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n645 SN74AS870]
|- {{anchor|74871}}
| 74x871
| 1
| 2个 16x4 register files
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n645 SN74AS871]
|- {{anchor|74873}}
| 74x873
| 2
| 2个 4-bit transparent latch with clear
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als873b SN74ALS873B]
|- {{anchor|74874}}
| 74x874
| 2
| 2个 4-bit edge-triggered D flip-flops with clear
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74as874 SN74ALS874]
|- {{anchor|74876}}
| 74x876
| 2
| 2个 4-bit edge-triggered D flip-flops with set, inverting outputs
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74as874 SN74ALS876]
|- {{anchor|74877}}
| 74x877
| 1
| 8-bit universal transceiver port controller
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n663 SN74AS877]
|- {{anchor|74878}}
| 74x878
| 2
| 2个 4-bit D-type flip-flop, synchronous clear, non-inverting outputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n669 SN74ALS878]
|- {{anchor|74879}}
| 74x879
| 2
| 2个 4-bit D-type flip-flop, synchronous clear, inverting outputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n669 SN74ALS879]
|- {{anchor|74880}}
| 74x880
| 2
| 2个 4-bit transparent latch with clear, inverting outputs
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n675 SN74ALS880]
|- {{anchor|74881}}
| 74x881
| 1
| 4-bit arithmetic logic unit
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n681 SN74AS881A]
|- {{anchor|74882}}
| 74x882
| 1
| 32-bit lookahead carry generator
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n683 SN74AS882]
|- {{anchor|74885}}
| 74x885
| 1
| 8-bit magnitude comparator
|
|
| 24
| [https://web.archive.org/web/20170403014245/http://www.ti.com/lit/ds/symlink/sn74as885.pdf SN74AS885]
|- {{anchor|74887}}
| 74x887
| 1
| 8-bit processor element (non-cascadable version of 74x888)
|
|
| (68)
| [https://archive.org/details/bitsavers_tidataBook_28346484/1986_LSI_Logic/page/n277 SN74AS887]
|- {{anchor|74888}}
| {{anchor|54888<!-- multiple anchors in |-  table element don't work, hence moved one anchor here -->}}74x888
| 1
| 8-bit [[slice processor|processor slice]]
|
|
| 64
| [https://archive.org/details/bitsavers_tidataBook_28346484/1986_LSI_Logic/page/n325 SN74AS888]
|- {{anchor|74889}}
| 74x889
| 1
| 8-bit [[slice processor|processor slice]]
|
|
| (68)
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n637 SN74AS889]
|- {{anchor|74890}}
| 74x890
| 1
| microoperation sequencer
|
|
| 64
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n375 SN74AS890]
|- {{anchor|74891}}
| 74x891
| 1
| microoperation sequencer
|
|
| (68)
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n685 SN74AS891]
|- {{anchor|74895}}
| 74x895
| 1
| 8-bit memory address generator
|
|
| (68)
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n393 SN74AS895]
|- {{anchor|74897}}
| 74x897
| 1
| 16-bit parallel/serial barrel shifter
|
|
| (68)
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n443 SN74AS897A]
|- {{anchor|74899}}
| 74x899
| 1
| 9-bit latchable transceiver with parity generator / checker
|
| 三态逻辑
| (28)
| [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n431 74AC899]
|-
! {{TOC tab|Part number|74x900 – 74x999}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|- {{anchor|74900}}
| 74x900
| 4
| 4个 2输入 NAND与非门
|
| driver
| 14
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0051456.pdf SN74ALS900]
|- {{anchor|74901}}
| 74x901
| 6
| 6个 inverting TTL buffer
|
|
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n93 MM74C901]
|- {{anchor|74902}}
| 74C902
| 6
| 6个 non-inverting TTL buffer
|
|
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n93 MM74C902]
|-
| 74ALS902
| 4
| 4个 2输入 NOR 或非门
|
| driver
| 14
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036721.pdf SN74ALS902]
|- {{anchor|74903}}
| 74C903
| 6
| 6个 inverting PMOS buffer
|
|
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n93 MM74C903]
|-
| 74ALS903
| 4
| 4个 2输入 NAND与非门
|
| open-collector driver
| 14
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036722.pdf SN74ALS903]
|- {{anchor|74904}}
| 74x904
| 6
| 6个 non-inverting PMOS buffer
|
|
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n93 MM74C904]
|- {{anchor|74905}}
| 74x905
| 1
| 12-bit successive approximation register
|
|
| 24
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n97 MM74C905]
|- {{anchor|74906}}
| 74x906
| 6
| 6个 open drain n-channel buffers
|
| open-collector
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n103 MM74C906]
|- {{anchor|74907}}
| 74x907
| 6
| 6个 open drain p-channel buffers
|
| {{Unknown|{{sp}}}}
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n103 MM74C907]
|- {{anchor|74908}}
| 74x908
| 2
| 2个 2输入 NAND 30&nbsp;V / 250&nbsp;mA relay driver
|
| {{Unknown|{{sp}}}}
| 8
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n105 MM74C908]
|- {{anchor|74909}}
| 74x909
| 4
| 4个 voltage comparator
| analog
| open-collector
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n109 MM74C909]
|- {{anchor|74910}}
| 74x910
| 1
| 256-bit RAM (64x4)
|
| 三态逻辑
| 18
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n115 MM74C910]
|- {{anchor|74911}}
| 74x911
| 1
| 4-digit expandable display controller
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n135 MM74C911]
|- {{anchor|74912}}
| 74x912
| 1
| 6-digit BCD display controller and driver
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n135 MM74C912]
|- {{anchor|74913}}
| 74x913
| 1
| 6-digit BCD display controller and driver, no decimal point
|
|
| 24
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n135 MM74C913]
|- {{anchor|74914}}
| 74x914
| 6
| 6个 非门, extended input voltage
| Schmitt trigger
|
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n117 MM74C914]
|- {{anchor|74915}}
| 74x915
| 1
| 7-segment to BCD converter
|
| 三态逻辑
| 18
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n141 MM74C915]
|- {{anchor|74917}}
| 74x917
| 1
| 6-digit 6个 display controller and driver
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1333 MM74C917]
|- {{anchor|74918}}
| 74x918
| 2
| 2个 2输入 NAND 30&nbsp;V / 250&nbsp;mA relay driver
|
| {{Unknown|{{sp}}}}
| 14
| [https://archive.org/details/bitsavers_nationaldaCMOSIntegratedCircuits_16413029/page/nal_CMOS_Integrated_Circuits#page/n105 MM74C918]
|- {{anchor|74920}}
| 74x920
| 1
| 1024-bit RAM (256x4), separate data inputs and outputs
|
| 三态逻辑
| 22
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n145 MM74C920]
|- {{anchor|74921}}
| 74x921
| 1
| 1024-bit RAM (256x4)
|
| 三态逻辑
| 18
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n145 MM74C921]
|- {{anchor|74922}}
| 74x922
| 1
| 16-key encoder
|
| 三态逻辑
| 18
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n149 MM74C922]
|- {{anchor|74923}}
| 74x923
| 1
| 20-key encoder
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n149 MM74C923]
|- {{anchor|74925}}
| 74x925
| 1
| 4-digit counter/display driver
|
|
| 16
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C925]
|- {{anchor|74926}}
| 74x926
| 1
| 4-digit decade counter/display driver, carry out and latch (up to 9999)
|
|
| 16
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C926]
|- {{anchor|74927}}
| 74x927
| 1
| 4-digit timer counter/display driver (up to 9599, intended as time elapsed, i.e. 9:59.9 min)
|
|
| 16
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C927]
|- {{anchor|74928}}
| 74x928
| 1
| 4-digit counter/display driver (up to 1999)
|
|
| 16
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C928]
|- {{anchor|74929}}
| 74x929
| 1
| 1024-bit RAM (1024x1), single chip select
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C929]
|- {{anchor|74930}}
| 74x930
| 1
| 1024-bit RAM (1024x1), three chip selects
|
| 三态逻辑
| 18
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n155 MM74C930]
|- {{anchor|74932}}
| 74x932
| 1
| [[phase comparator]]
|
|
| 8
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1305 MM74C932]
|- {{anchor|74933}}
| 74x933
| 1
| 7-bit address bus comparator
|
|
| 20
| [https://archive.org/stream/NationalSemiconductor-CMOSDatabook1981#page/n5 MM74C933]
|- {{anchor|74934}}
| 74934
| 1
| ADC similar to ADC0829, see corresponding NSC datasheet
|
|
|
|
|- {{anchor|74935}}
| 74x935
| 1
| [[Analog-to-digital converter|ADC]] for 3.5-digit digital [[voltmeter]]s, multiplexed 7-segment display outputs
| analog
|
| 28
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/nal_CMOS_Databook#page/n163 MM74C935]
|- {{anchor|74936}}
| 74x936
| 1
| ADC for 3.75-digit digital voltmeters, multiplexed 7-segment display outputs
| analog
|
| {{Unknown|{{?}}}}
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/n171 MM74C936]
|- {{anchor|74937}}
| 74x937
| 1
| ADC for 3.5-digit digital voltmeters, multiplexed BCD outputs
| analog
|
| 24
| [https://archive.org/details/bitsavers_nationaldaDataAcquisitionHandbook_38492992/page/n83 MM74C937]
|- {{anchor|74938}}
| 74x938
| 1
| ADC for 3.75-digit digital voltmeters, multiplexed BCD outputs
| analog
|
| 24
| [https://archive.org/details/bitsavers_nationaldaDataAcquisitionHandbook_38492992/page/n83 MM74C938]
|- {{anchor|74940}}
| 74x940
| 1
| 8个 bus/line drivers/line receivers
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n161 DM74S940]
|- {{anchor|74941}}
| 74x941
| 1
| 8个 bus/line drivers/line receivers
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n161 DM74S941]
|- {{anchor|74942}}
| 74x942
| 1
| 300 baud [[Bell 103 modem]] (+/- 5&nbsp;V supply)
|
|
| 20
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n639 MM74HC942]
|- {{anchor|74943}}
| 74x943
| 1
| 300 baud [[Bell 103 modem]] (single 5&nbsp;V supply)
|
|
| 20
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n645 MM74HC943]
|- {{anchor|74945}}
| 74x945
| 1
| 4-digit up/down counter, decoder and LCD driver, output latch
|
|
| 40
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1343 MM74C945]
|- {{anchor|74946}}
| 74x946
| 1
| 4.5-digit counter, decoder and LCD driver, leading zero blanking
|
|
| 40
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1351 MM74C946]
|- {{anchor|74947}}
| 74x947
| 1
| 4-digit up/down counter, decoder and LCD driver, leading zero blanking
|
|
| 40
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1343 MM74C947]
|- {{anchor|74948}}
| 74x948
| 1
| 8-bit [[Analog-to-digital converter|ADC]] with 16-channel analog multiplexer
| analog
| 三态逻辑
| 40
| [https://archive.org/details/bitsavers_nationaldaDataAcquisitionHandbook_38492992/page/n63 MM74C948]
|- {{anchor|74949}}
| 74x949
| 1
| 8-bit [[Analog-to-digital converter|ADC]] with 8-channel analog multiplexer
| analog
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/n173 MM74C949]
|- {{anchor|74950}}
| 74x950
| 1
| 8-bit [[Analog-to-digital converter|ADC]] with 8-channel analog multiplexer and [[sample and hold]]
| analog
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_nationaldaCMOSDatabook_23595721/page/n173 MM74C950]
|- {{anchor|74952}}
| 74x952
| 1
| 2个 rank 8-bit shift register, synchronous clear
|
| 三态逻辑
| 18
| [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n417 DM74LS952]
|- {{anchor|74956}}
| 74C956
| 1
| 4-digit, 17-segment alpha-numeric LED display driver with memory and decoder
|
|
| 40
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1357 MM74C956]
|-
| 74BCT956
| 1
| 8个 bus transceiver and latch
|
| 三态逻辑
| 24
| [https://datasheetspdf.com/pdf-file/1271601/Texas/SN74BCT956/1 SN74BCT956]
|- {{anchor|74962}}
| 74x962
| 1
| 2个 rank 8-bit shift register, register exchange mode
|
| 三态逻辑
| 18
| [https://archive.org/stream/NationalSemiconductorLogicDatabook1981/National%20Semiconductor%20Logic%20Databook%201981#page/n417 DM74LS962]
|- {{anchor|74963}}
| 74x963
| 1
| 2个 rank 8-bit shift register, synchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n461 SN74ALS963]
|- {{anchor|74964}}
| 74x964
| 1
| 2个 rank 8-bit shift register, synchronous and asynchronous clear
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n461 SN74ALS964]
|- {{anchor|74968}}
| 74x968
| 1
| controller/driver for 16k/64k/256k/1M dRAM
|
|
| 52
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n655 74F968]
|- {{anchor|74978}}
| 74x978
| 1
| 8个 flip-flop with serial scanner
|
|
| 24
| [https://archive.org/stream/NationalSemiconductor1988FASTAdvancedSchottkyDatabook/National%20Semiconductor%201988%20FAST%20Advanced%20Schottky%20Databook#page/n667 74F978]
|- {{anchor|74979}}
| 74x979
| 1
| 9-bit registered transceiver with parity generator/checker for [[FutureBus]]
|
| 三态逻辑 and open-collector
| (48)
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n447 SN74BCT979]
|- {{anchor|74989}}
| 74x989
| 1
| 64-bit RAM (64x4), inverting output
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n1313 MM74C989]
|- {{anchor|74990}}
| 74x990
| 1
| 8-bit D-type transparent read-back latch, non-inverting
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als990 SN74ALS990]
|- {{anchor|74991}}
| 74x991
| 1
| 8-bit D-type transparent read-back latch, inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n473 SN74ALS991]
|- {{anchor|74992}}
| 74x992
| 1
| 9-bit D-type transparent read-back latch, non-inverting
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als992 SN74ALS992]
|- {{anchor|74993}}
| 74x993
| 1
| 9-bit D-type transparent read-back latch, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n481 SN74ALS993]
|- {{anchor|74994}}
| 74x994
| 1
| 10-bit D-type transparent read-back latch, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n489 SN74ALS994]
|- {{anchor|74995}}
| 74x995
| 1
| 10-bit D-type transparent read-back latch, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n489 SN74ALS995]
|- {{anchor|74996}}
| 74x996
| 1
| 8-bit D-type edge-triggered read-back latch
|
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74als996 SN74ALS996]
|-
! {{TOC tab|Part number|74x1000 – 74x1999}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x1000
| 4
| 4个 2输入 NAND与非门
|
| driver
| 14
| [http://www.ti.com/lit/gpn/sn54as1000a SN74AS1000A]
|-
| 74x1002
| 4
| 4个 2输入 NOR 或非门
|
| driver
| 14
| [http://www.ti.com/lit/gpn/sn54als1002a SN74ALS1002A]
|-
| 74x1003
| 4
| 4个 2输入 NAND与非门
|
| open-collector driver
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n701 SN74ALS1003A]
|-
| 74x1004
| 6
| 6个 inverting buffer
|
| driver
| 14
| [http://www.ti.com/lit/gpn/sn74als1004 SN74ALS1004]
|-
| 74x1005
| 6
| 6个 inverting buffer
|
| open-collector driver
| 14
| [http://www.ti.com/lit/gpn/sn74als1005 SN74ALS1005]
|-
| 74x1008
| 4
| 4个 2输入 AND与门
|
| driver
| 14
| [http://www.ti.com/lit/gpn/sn74as1008a SN74AS1008A]
|-
| 74ALS1010
| 3
| 3个 3输入 NAND与非门
|
| driver
| 14
| [https://web.archive.org/web/20170225141918/http://www.ti.com/lit/ds/symlink/sn74als1010a.pdf SN74ALS1010A]
|-
| 74AC1010,<br/>74ACT1010
| 1
| 16x16-bit multiplier/accumulator
|
| 三态逻辑
| 64
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n457 74AC1010]
|-
| 74x1011
| 3
| 3个 3输入 AND与门
|
| driver
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n715 SN74ALS1011A]
|-
| 74F1016
| 16
| 16-bit Schottky diode R-C bus termination array
|
| {{Unknown|{{sp}}}}
| (20)
| [http://www.ti.com/lit/gpn/sn74f1016 SN74F1016]
|-
| 74AC1016,<br/>74ACT1016
| 1
| 16x16-bit multiplier
|
| 三态逻辑
| 64
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n467 74AC1016]
|-
| 74x1017
| 1
| 16x16-bit parallel multiplier
|
| 三态逻辑
| 64
| [https://archive.org/details/bitsavers_fairchilddldFACTLogicDataBook_27153725/page/n479 74AC1017]
|-
| 74x1018
| 18
| 18-bit Schottky diode R-C bus termination array
|
| {{Unknown|{{sp}}}}
| (24)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-706945.pdf SN74F1018]
|-
| 74x1020
| 2
| 2个 4输入 NAND与非门
|
| driver
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n717 SN74ALS1020A]
|-
| 74x1032
| 4
| 4个 2输入  OR或门
|
| driver
| 14
| [https://web.archive.org/web/20170221113739/http://www.ti.com/lit/ds/symlink/sn74as1032a.pdf SN74AS1032A]
|-
| 74x1034
| 6
| 6个 non-inverting buffer
|
| driver
| 14
| [http://www.ti.com/lit/gpn/sn54als1034 SN74ALS1034]
|-
| 74x1035
| 6
| 6个 non-inverting buffer
|
| open-collector driver
| 14
| [http://www.ti.com/lit/gpn/sn54als1035 SN74ALS1035]
|-
| 74x1036
| 4
| 4个 2输入 NOR 或非门
|
| driver
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n729 SN74ALS1036]
|-
| 74x1050
| 12
| 12-bit Schottky diode bus termination array, clamp to GND
|
| {{Unknown|{{sp}}}}
| 16
| [http://www.ti.com/lit/gpn/sn74s1050 SN74S1050]
|-
| 74x1051
| 12
| 12-bit Schottky diode bus termination array, clamp to GND/V<sub>CC</sub>
|
| {{Unknown|{{sp}}}}
| 16
| [http://www.ti.com/lit/gpn/sn74s1051 SN74S1051]
|-
| 74x1052
| 16
| 16-bit Schottky diode bus termination array, clamp to GND
|
| {{Unknown|{{sp}}}}
| 20
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n471 SN74S1052]
|-
| 74x1053
| 16
| 16-bit Schottky diode bus termination array, clamp to GND/V<sub>CC</sub>
|
| {{Unknown|{{sp}}}}
| 20
| [http://www.ti.com/lit/gpn/sn74s1053 SN74S1053]
|-
| 74x1056
| 8
| 8-bit Schottky diode bus termination array, clamp to GND
|
| {{Unknown|{{sp}}}}
| (16)
| [http://www.ti.com/lit/gpn/sn74f1056 SN74F1056]
|-
| 74x1071
| 10
| 10-bit bus termination array with bus-hold function
|
|
| (14)
| [http://www.ti.com/lit/gpn/sn74act1071 SN74ACT1071]
|-
| 74x1073
| 16
| 16-bit bus termination array with bus-hold function
|
|
| (20)
| [http://www.ti.com/lit/gpn/sn74act1073 SN74ACT1073]
|-
| 74x1074
| 2
| 2个 D negative edge triggered flip-flop, asynchronous preset and clear
|
|
| 14
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-210975.pdf 74FR1074]
|-
| 74x1181
| 1
| 4-bit arithmetic logic unit
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n503 SN74AS1181]
|-
| 74x1240
| 1
| 8个 buffer / line driver, inverting (lower-power version of 74x240)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n731 SN74ALS1240]
|-
| 74x1241
| 1
| 8个 buffer / line driver, non-inverting (lower-power version of 74x241)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n731 SN74ALS1241]
|-
| 74x1242
| 1
| 4个 bus transceiver, inverting (lower-power version of 74x242)
|
| 三态逻辑
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n735 SN74ALS1242]
|-
| 74x1243
| 1
| 4个 bus transceiver, non-inverting (lower-power version of 74x243)
|
| 三态逻辑
| 14
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n735 SN74ALS1243]
|-
| 74x1244
| 1
| 8个 buffer / driver, non-inverting (lower-power version of 74x244)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n739 SN74ALS1244]
|-
| 74x1245
| 1
| 8个 bus transceiver (lower-power version of 74x245)
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als1245a SN74ALS1245A]
|-
| 74x1280
| 1
| 9-bit parity generator/checker with registered outputs
|
| 三态逻辑
| 20
| [https://web.archive.org/web/20181117162114/https://4donline.ihs.com/images/VipMasterIC/IC/QSEM/QSEMD004/QSEMD004-3-71.pdf QS74FCT1280]
|-
| 74x1284
| 1
| parallel printer interface transceiver / buffer ([[IEEE 1284]])
|
|
| 20
| [http://pdf.datasheetcatalog.com/datasheet/philips/74HCT1284PW.pdf 74HCT1284]
|-
| 74x1403
| 1
| 8-bit bus receiver plus 4-bit bus driver
| Schmitt trigger
| 三态逻辑
| (32)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-25/DSA-497532.pdf 74LVT1403]
|-
| 74x1404
| 1
| oscillator driver
| Schmitt trigger
|
| (8)
| [http://www.ti.com/lit/gpn/sn74lvc1404 SN74LVC1404]
|-
| 74x1604
| 1
| 2个 8-bit transparent latch with output multiplexer
|
|
| 28
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F1604_PhilipsSemiconductors.pdf 74F1604]
|-
| 74x1616
| 1
| 16x16-bit multimode multiplier
|
| 三态逻辑
| 64
| [https://archive.org/details/bitsavers_icMaster19_159569496/page/n919 SN74ALS1616]
|-
| 74x1620
| 1
| 8个 bus transceiver, inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n747 SN74ALS1620]
|-
| 74x1621
| 1
| 8个 bus transceiver, non-inverting
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n747 SN74ALS1621]
|-
| 74x1622
| 1
| 8个 bus transceiver, inverting
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n747 SN74ALS1622]
|-
| 74x1623
| 1
| 8个 bus transceiver, non-inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n747 SN74ALS1623]
|-
| 74x1631
| 1
| 4个 bus driver with complementary outputs
|
| 三态逻辑
| 16
| SN74ALS1631<ref name=ttltb3/>{{rp|at=3-336}}
|-
| 74x1638
| 1
| 8个 bus transceiver, inverting (lower-power version of 74x638)
|
| 三态逻辑 and open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n753 SN74ALS1638]
|-
| 74x1639
| 1
| 8个 bus transceiver, non-inverting (lower-power version of 74x639)
|
| 三态逻辑 and open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n753 SN74ALS1639]
|-
| 74x1640
| 1
| 8个 bus transceiver, inverting (lower-power version of 74x640)
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als1645a SN74ALS1640A]
|-
| 74x1641
| 1
| 8个 bus transceiver, non-inverting (lower-power version of 74x641)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n757 SN74ALS641]
|-
| 74x1642
| 1
| 8个 bus transceiver, inverting (lower-power version of 74x642)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n757 SN74ALS642]
|-
| 74x1643
| 1
| 8个 bus transceiver, inverting and non-inverting (lower-power version of 74x643)
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n757 SN74ALS643]
|-
| 74x1644
| 1
| 8个 bus transceiver, inverting and non-inverting (lower-power version of 74x644)
|
| open-collector
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n757 SN74ALS644]
|-
| 74x1645
| 1
| 8个 bus transceiver, non-inverting (lower-power version of 74x645)
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74als1645a SN74ALS1645A]
|-
| 74x1650
| 2
| 2个 9-bit [[Futurebus]] universal storage transceiver with split TTL I/O
|
| 三态逻辑 and open-collector
| (100)
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n689 SN74FB1650]
|-
| 74x1651
| 2
| 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split TTL I/O
|
| 三态逻辑 and open-collector
| (100)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-703111.pdf SN74FB1651]
|-
| 74x1653
| 2
| 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split 3.3V TTL I/O
|
| 三态逻辑 and open-collector
| (100)
| [http://www.ti.com/lit/gpn/SN74FB1653 SN74FB1653]
|-
| 74x1665
| 2
| 2个 8-bit [[Gunning transceiver logic|GTL]] universal storage transceivers with live insertion
|
| 三态逻辑 and open-collector
| (64)
| [http://www.ti.com/lit/gpn/SN74GTL1655 SN74GTL1655]
|-
| 74x1760
| 1
| 10-bit 4-way latched address multiplexer
|
| 三态逻辑
| 64
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0034403.pdf 74F1760]
|-
| 74x1761
| 1
| dRAM and interrupt vector controller
|
|
| 48
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n911 74F1761]
|-
| 74x1762
| 1
| dRAM address controller
|
|
| 40
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n913 74F1762]
|-
| 74x1763
| 1
| 1个-port dRAM controller
|
|
| 48
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n915 74F1763]
|-
| 74x1764
| 1
| 2个-port dRAM controller
|
|
| 48
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n917 74F1764]
|-
| 74x1765
| 1
| 2个-port dRAM controller with address latch
|
|
| 48
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n917 74F1765]
|-
| 74x1766
| 1
| burst mode dRAM controller
|
|
| 48
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-054/DSAIH00097122.pdf 74F1766]
|-
| 74x1779
| 1
| 8-bit bidirectional binary counter
|
| 三态逻辑
| 16
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F1779_PhilipsSemiconductors.pdf 74F1779]
|-
| 74x1801
| 1
| [[Frequency modulation|FM]], [[Modified Frequency Modulation|MFM]], and [[Differential Manchester encoding|DM]] encoder / decoder, data rates up to 10&nbsp;MHz
|
|
| 24
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-002/Scans-0052487.pdf 74LS1801]
|-
| 74x1802
| 1
| [[SerDes]] with [[Error correction code|ECC]] and [[Cyclic redundancy check|CRC]], data rates up to 10&nbsp;MHz
|
| 三态逻辑
| 48
| [https://4donline.ihs.com/images/VipMasterIC/IC/SIGC/SIGCD005/SIGCD005-7-26.pdf 74LS1802]
|-
| 74x1803
| 1
| 4个 clock driver
|
|
| 14
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/n309 MC74F1803]
|-
| 74x1804
| 6
| 6个 2输入 NAND
|
| driver
| 20
| [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n639 DM74AS1804]
|-
| 74x1805
| 6
| 6个 2输入 NOR
|
| driver
| 20
| [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n641 DM74AS1805]
|-
| 74x1808
| 6
| 6个 2输入 AND
|
| driver
| 20
| [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n643 DM74AS1808]
|-
| 74x1811
| 1
| [[Frequency modulation|FM]], [[Modified Frequency Modulation|MFM]], and [[Differential Manchester encoding|DM]] encoder / decoder, data rates up to 20&nbsp;MHz
|
|
| 24
| [https://4donline.ihs.com/images/VipMasterIC/IC/SIGC/SIGCD005/SIGCD005-7-36.pdf 74LS1811]
|-
| 74x1812
| 1
| [[SerDes]] with [[Error correction code|ECC]] and [[Cyclic redundancy check|CRC]], data rates up to 30&nbsp;MHz
|
| 三态逻辑
| 48
| [https://4donline.ihs.com/images/VipMasterIC/IC/SIGC/SIGCD005/SIGCD005-7-37.pdf 74LS1812]
|-
| 74x1821
| 1
| 10-bit bus interface flip-flops
|
| 三态逻辑
| 24
| [http://www.elektronikjk.pl/elementy_czynne/IC/SN74AS1821.pdf SN74AS1821]
|-
| 74x1823
| 1
| 9-bit bus interface flip-flops with clear
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00218035.pdf SN74AS1823]
|-
| 74x1832
| 6
| 6个 2输入 OR
|
| driver
| 20
| [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n645 DM74ALS1832]
|-
| 74x1841
| 1
| 10-bit bus interface transparent latches
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00218036.pdf SN74AS1841]
|-
| 74x1843
| 1
| 9-bit bus interface transparent latches with clear
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-706295.pdf SN74AS1843]
|-
! {{TOC tab|Part number|74x2000 – 74x2999}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x2000
| 1
| direction discriminator with microprocessor interface
|
| 三态逻辑
| 28
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-110/22.pdf SN74LS2000]
|-
| 74x2003
| 1
| 8-bit level translator
|
| {{unknown|{{sp}}}}
| (20)
| [http://www.ti.com/lit/gpn/SN74GTL2003 SN74GTL2003]
|-
| 74x2006
| 1
| 13-bit [[Gunning transceiver logic|GTL]] to 3.3V TTL level translator
|
| open-collector
| (28)
| [http://www.ti.com/lit/gpn/SN74GTL2006 SN74GTL2006]
|-
| 74x2007
| 1
| 12-bit [[Gunning transceiver logic|GTL]] to 3.3V TTL level translator
|
| open-collector
| (28)
| [http://www.ti.com/lit/gpn/SN74GTL2007 SN74GTL2007]
|-
| 74x2010
| 1
| 10-bit level translator
|
| {{unknown|{{sp}}}}
| (24)
| [http://www.ti.com/lit/gpn/SN74GTL2010 SN74GTL2010]
|-
| 74x2014
| 1
| 4-bit [[Gunning transceiver logic|GTL]] to TTL transceiver
|
| 三态逻辑 and open-collector
| (14)
| [http://www.ti.com/lit/gpn/SN74GTL2014 SN74GTL2014]
|-
| 74x2031
| 1
| 9-bit [[Futurebus]] address/data transceiver
|
| 三态逻辑 and open-collector
| (48)
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n695 SN74FB2031]
|-
| 74x2032
| 1
| 9-bit [[Futurebus]] competition transceiver
|
| 三态逻辑 and open-collector
| (48)
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n701 SN74FB2032]
|-
| 74x2033
| 1
| 8-bit [[Futurebus]] registered transceiver with split TTL I/O
|
| 三态逻辑 and open-collector
| (52)
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n709 SN74FB2033]
|-
| 74x2040
| 1
| 8-bit [[Futurebus]] transceiver with split TTL I/O
|
| 三态逻辑 and open-collector
| (48)
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n719 SN74FB2040]
|-
| 74x2041
| 1
| 7-bit [[Futurebus]] transceiver with split TTL I/O
|
| 三态逻辑 and open-collector
| (52)
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n725 SN74FB2041]
|-
| 74x2107
| 1
| 12-bit [[Gunning transceiver logic|GTL]] to 3.3V TTL level translator
|
| open-collector
| (28)
| [http://www.ti.com/lit/gpn/SN74GTL2107 SN74GTL2107]
|-
| 74x2125
| 4
| 4个 bus buffer
|
| 三态逻辑, 25&nbsp;Ω series resistor
| (14)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-2/DSA-33230.pdf TC74VCX2125]
|-
| 74x2140
| 1
| 8k x 18 cache data RAM
|
| 三态逻辑
| (52)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2140A]
|-
| 74x2150
| 1
| 512 x 8 cache address comparator
|
|
| 24
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2150A]
|-
| 74ACT2151
| 1
| 1k x 11 cache address comparator
|
|
| 28
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2151]
|-
| 74FCT2151
| 1
| 8-line to 1-line multiplexer
|
| 25&nbsp;Ω series resistor
| (16)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n187 CD74FCT2151]
|-
| 74x2152
| 1
| 2k x 8 cache address comparator
|
|
| 28
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2152A]
|-
| 74ACT2153
| 1
| 1k x 11 cache address comparator
|
| open-collector
| 28
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2153]
|-
| 74FCT2153
| 2
| 2个 4-line to 1-line multiplexer
|
| 25&nbsp;Ω series resistor
| (16)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n191 CD74FCT2153]
|-
| 74x2154
| 1
| 2k x 8 cache address comparator
|
| open-collector
| 28
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2154A]
|-
| 74x2155
| 1
| 2k x 8 burst cache address comparator
|
| 三态逻辑
| (44)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2155]
|-
| 74x2156
| 1
| 16k x 4 burst cache address comparator
|
| 三态逻辑
| (44)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2156]
|-
| 74ACT2157
| 1
| 2k x 16 cache address comparator
|
| 三态逻辑
| (44)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2157]
|-
| 74FCT2157
| 4
| 4个 2-line to 1-line multiplexer
|
| 25&nbsp;Ω series resistor
| (16)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n197 CD74FCT2157]
|-
| 74x2158
| 1
| 8k x 9 cache address comparator
|
| 三态逻辑
| (44)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2158]
|-
| 74x2159
| 1
| 8k x 9 cache address comparator
|
| 三态逻辑
| (44)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2159]
|-
| 74x2160
| 1
| 8k x 4 2-way cache address comparator
|
| 三态逻辑
| (32)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2160]
|-
| 74x2161
| 1
| synchronous presettable 4-bit binary counter, asynchronous clear
|
| 25&nbsp;Ω series resistor
| 16
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n313 QS74FCT2161T]
|-
| 74ACT2163,<br />74BCT2163
| 1
| 16k x 5 cache address comparator
|
| 三态逻辑
| (32)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2163]
|-
| 74FCT2163
| 1
| synchronous presettable 4-bit binary counter, synchronous clear
|
| 25&nbsp;Ω series resistor
| 16
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n313 QS74FCT2163T]
|-
| 74x2164
| 1
| 16k x 5 cache address comparator
|
| 三态逻辑
| (32)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT2164]
|-
| 74x2166
| 1
| 16k x 5 cache address comparator with input latches
|
| 三态逻辑
| (32)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74BCT2166]
|-
| 74x2191
| 1
| synchronous presettable 4-bit binary up/down counter, common clock
|
| 25&nbsp;Ω series resistor
| 16
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n321 QS74FCT2191T]
|-
| 74x2193
| 1
| synchronous presettable 4-bit binary counter, separate up/down clocks
|
| 25&nbsp;Ω series resistor
| 16
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n329 QS74FCT2193T]
|-
| 74x2226
| 2
| 2个 64-bit FIFO memories (64x1)
|
|
| (24)
| [http://www.ti.com/lit/gpn/sn74act2226 SN74ACT2226]
|-
| 74x2227
| 2
| 2个 64-bit FIFO memories (64x1)
|
| 三态逻辑
| (28)
| [http://www.ti.com/lit/gpn/sn74act2227 SN74ACT2227]
|-
| 74x2228
| 2
| 2个 256-bit FIFO memories (256x1)
|
|
| (24)
| [http://www.ti.com/lit/gpn/sn74act2226 SN74ACT2228]
|-
| 74x2229
| 2
| 2个 256-bit FIFO memories (256x1)
|
| 三态逻辑
| (28)
| [http://www.ti.com/lit/gpn/sn74act2227 SN74ACT2229]
|-
| 74x2232
| 1
| 512-bit FIFO memory (64x8)
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n167 SN74ALS2232A]
|-
| 74x2233
| 1
| 576-bit FIFO memory (64x9)
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n175 SN74ALS2233A]
|-
| 74x2235
| 1
| 18432-bit bidirectional FIFO memory (2x1024x9)
|
| 三态逻辑
| (44)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n203 SN74ACT2235]
|-
| 74x2236
| 1
| 18432-bit bidirectional FIFO memory (2x1024x9)
|
| 三态逻辑
| (44)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n215 SN74ACT2236]
|-
| 74x2238
| 1
| 576-bit bidirectional FIFO memory (2x32x9)
|
| 三态逻辑
| 40
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n157 SN74ALS2238]
|-
| 74x2240
| 2
| 2个 4-bit bidirectional buffer / line driver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n81 SN74BCT2240]
|-
| 74x2241
| 2
| 2个 4-bit bidirectional buffer / line driver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n85 SN74BCT2241]
|-
| 74x2242
| 1
| 4-bit bus transceiver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 14
| [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n951 SN74ALS2242]
|-
| 74x2243
| 1
| 4-bit bus transceiver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| (14)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-209724.pdf 74F2243]
|-
| 74x2244
| 2
| 2个 4-bit buffer / line driver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n89 SN74BCT2244]
|-
| 74x2245
| 1
| 8个 bus transceiver
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n599 SN74ABT2245]
|-
| 74x2253
| 2
| 2个 4-line to 1-line multiplexer
|
| 三态逻辑, 25&nbsp;Ω series resistor
| (16)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n191 CD74FCT2253]
|-
| 74x2257
| 4
| 4个 2-line to 1-line multiplexer
|
| 三态逻辑, 25&nbsp;Ω series resistor
| (16)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n197 CD74FCT2257]
|-
| 74x2273
| 8
| 8个 D-type flip-flop with common clock and reset
|
| 25&nbsp;Ω series resistor
| (20)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n215 CD74FCT2273]
|-
| 74x2299
| 1
| 8-bit universal shift register
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n363 QS74FCT2299T]
|-
| 74x2323
| 2
| 2个 line receiver
| {{unknown|analog}}
|
| (8)
| [http://www.ti.com/lit/gpn/sn74ls2323 SN74LS2323]
|-
| 74x2373
| 1
| 8-bit transparent latch
|
| 三态逻辑, 25&nbsp;Ω series resistor
| (20)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n219 CD74FCT2373]
|-
| 74x2374
| 8
| 8个 D-type flip-flop with common clock
|
| 三态逻辑, 25&nbsp;Ω series resistor
| (20)
| [https://archive.org/details/bitsavers_harrisdataCTLogic_25505286/page/n227 CD74FCT2374]
|-
| 74x2377
| 1
| 8-bit register with clock enable
|
| 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n381 QS74FCT2377T]
|-
| 74x2400
| 2
| 2个 4-bit buffer, inverting
| Schmitt trigger
| 三态逻辑
| 20
| [http://www.ic72.com/pdf_file/i/189451.pdf 74THC2400]
|-
| 74x2410
| 1
| 11-bit MOS memory driver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 28
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n747 SN74BCT2410]
|-
| 74x2411
| 1
| 11-bit MOS memory driver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 28
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n749 SN74BCT2411]
|-
| 74x2414
| 2
| 2个 2-to-4 line decoder with supply voltage monitor
|
|
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-17/DSA-337707.pdf SN74BCT2414]
|-
| 74x2420
| 1
| 16-bit [[NuBus]] address/data transceiver and register
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n29 SN74BCT2420]
|-
| 74x2423
| 1
| 16-bit latched multiplexer/demultiplexer [[NuBus]] transceiver, inverting
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n39 SN74BCT2423]
|-
| 74x2424
| 1
| 16-bit latched multiplexer/demultiplexer [[NuBus]] transceiver, non-inverting
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n39 SN74BCT2424]
|-
| 74x2425
| 1
| [[Macintosh]] Coprocessor Platform [[NuBus]] address/data registered transceiver
|
| 三态逻辑
| (100)
| [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n49 SN74BCT2425]
|-
| 74x2440
| 1
| [[NuBus]] interface controller
|
|
| (68)
| [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n61 SN74ACT2440]
|-
| 74x2441
| 1
| [[NuBus]] interface controller
|
|
| (100)
| [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n93 SN74ACT2441]
|-
| 74x2442
| 1
| [[NuBus]] block slave address generator
|
| 三态逻辑
| (20)
| [https://archive.org/details/bitsavers_tidataBookProducts_10042209/page/n145 SN74ALS2442]
|-
| 74x2509
| 1
| 9-output clock driver with [[Phase-locked loop|PLL]]
|
| 三态逻辑
| (24)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-13/DSA-248016.pdf HD74CDC2509]
|-
| 74x2510
| 1
| 10-output clock driver with [[Phase-locked loop|PLL]]
|
| 三态逻辑
| (24)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-13/DSA-248017.pdf HD74CDC2510]
|-
| 74x2525
| 1
| 8-output clock driver
|
|
| 14
| [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n443 74AC2525]
|-
| 74x2526
| 1
| 8-output clock driver with input multiplexer
|
|
| 16
| [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n443 74AC2526]
|-
| 74x2533
| 1
| 8-bit bus interface latch, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n369 QS74FCT2533T]
|-
| 74x2534
| 1
| 8-bit bus interface register, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n375 QS74FCT2534T]
|-
| 74x2540
| 1
| 8-bit buffer / line driver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n955 SN74ALS2540]
|-
| 74x2541
| 1
| 8-bit buffer / line driver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBooktaBook_60160366/page/n955 SN74ALS2541]
|-
| 74x2543
| 1
| 8-bit latched transceiver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n399 QS74FCT2543T]
|-
| 74x2544
| 1
| 8-bit latched transceiver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n399 QS74FCT2544T]
|-
| 74x2573
| 1
| 8-bit transparent latch
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n407 QS74FCT2573T]
|-
| 74x2574
| 8
| 8个 D-type flip-flop with common clock
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n413 QS74FCT2574T]
|-
| 74x2620
| 1
| 8个 bus transceiver / MOS driver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n763 SN74AS2620]
|-
| 74x2623
| 1
| 8个 bus transceiver / MOS driver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n763 SN74AS2623]
|-
| 74x2640
| 1
| 8个 bus transceiver / MOS driver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n767 SN74AS2640]
|-
| 74x2643
| 1
| 8个 bus transceiver, mix of inverting and non-inverting outputs
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-22/DSA-425742.pdf 74F2643]
|-
| 74x2645
| 1
| 8个 bus transceiver / MOS driver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 20
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n767 SN74AS2645]
|-
| 74x2646
| 1
| 8个 registered transceiver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n419 QS74FCT2646T]
|-
| 74x2648
| 1
| 8个 registered transceiver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n419 QS74FCT2648T]
|-
| 74x2651
| 1
| 8个 registered transceiver, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n427 QS74FCT2651T]
|-
| 74x2652
| 1
| 8个 registered transceiver, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n427 QS74FCT2652T]
|-
| 74S2708
| 1
| 8192-bit PROM (1024x8)
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/n177 SN74S2708]
|-
| 74AC2708
| 1
| 576-bit FIFO memory (64x9)
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n445 74AC2708]
|-
| 74x2725
| 1
| 4608-bit FIFO memory (512x9)
|
|
| 28
| [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n461 74ACT2725]
|-
| 74x2726
| 1
| 4608-bit bidirectional FIFO memory (512x9)
|
|
| 28
| [https://archive.org/details/bitsavers_nationaldaFACTDatabook_39311242/page/n461 74ACT2726]
|-
| 74x2821
| 1
| 10-bit D-type flip-flop
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n435 QS74FCT2821T]
|-
| 74x2823
| 1
| 9-bit D-type flip-flop with clear
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n435 QS74FCT2823T]
|-
| 74x2825
| 1
| 8-bit D-type flip-flop with clear and clock enable
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n435 QS74FCT2825T]
|-
| 74x2827
| 1
| 10-bit buffer, non-inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n93 SN74BCT2827A]
|-
| 74x2828
| 1
| 10-bit buffer, inverting
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/bitsavers_tidataBookerfaceLogicDataBook_4501982/page/n93 SN74BCT2828A]
|-
| 74x2833
| 1
| 8-bit bus transceiver with parity error flip-flop
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n451 QS74FCT2833T]
|-
| 74x2841
| 1
| 10-bit transparent latch
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n453 QS74FCT2841T]
|-
| 74x2843
| 1
| 9-bit transparent latch with asynchronous reset
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n453 QS74FCT2843T]
|-
| 74x2845
| 1
| 8-bit transparent latch with asynchronous reset and multiple output enable
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n453 QS74FCT2845T]
|-
| 74x2853
| 1
| 8-bit bus transceiver with parity error latch
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n451 QS74FCT2853T]
|-
| 74x2861
| 1
| 10-bit non-inverting bus transceiver
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2861T]
|-
| 74x2862
| 1
| 10-bit inverting bus transceiver
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2862T]
|-
| 74x2863
| 1
| 9-bit non-inverting bus transceiver with 2个 output enable
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2863T]
|-
| 74x2864
| 1
| 9-bit inverting bus transceiver with 2个 output enable
|
| 三态逻辑, 25&nbsp;Ω series resistor
| 24
| [https://archive.org/details/QualitySemiconductor-1991DatabookOCR/page/n463 QS74FCT2864T]
|-
| 74x2952
| 1
| 8个 bus transceiver and register, non-inverting
|
| 三态逻辑
| 24
| [https://archive.org/stream/TexasInstrumentsLVCAndLVDataBook1998/Texas_Instruments_LVC_and_LV_Data_Book_1998#page/n391 SN74LVC2952A]
|-
| 74x2953
| 1
| 8个 bus transceiver and register, inverting
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n945 74F2953]
|-
| 74x2960{{anchor|742960}}
| 1
| [[error detection and correction]] (EDAC), equivalent to [[AMD Am2900#Members of the Am2900 family|Am2960]]
|
| 三态逻辑
| 48
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n629 MC74F2960]
|-
| 74x2961
| 1
| 4-bit EDAC bus buffer, inverting, equivalent to [[AMD Am2900#Members of the Am2900 family|Am2961]]
|
| 三态逻辑
| 24
| [https://datasheetspdf.com/pdf-file/501240/Motorola/MC74F2961A/1 MC74F2961A]
|-
| 74x2962
| 1
| 4-bit EDAC bus buffer, non-inverting, equivalent to [[AMD Am2900#Members of the Am2900 family|Am2962]]
|
| 三态逻辑
| 24
| [https://datasheetspdf.com/pdf-file/501240/Motorola/MC74F2961A/1 MC74F2962A]
|-
| 74x2967
| 1
| controller/driver for 16k/64k/256k dRAM
|
|
| 48
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n515 SN74ALS2967]
|-
| 74x2968
| 1
| controller/driver for 16k/64k/256k dRAM
|
|
| 48
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n515 SN74ALS2968]
|-
| 74x2969
| 1
| memory timing controller for use with [[error detection and correction|EDAC]]
|
|
| 48
| [https://archive.org/details/bitsavers_motoroladaSchottkyTTLData_33878952/page/n635 MC74F2969]
|-
| 74x2970
| 1
| memory timing controller for use without EDAC
|
|
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0043139.pdf MC74F2970]
|-
! {{TOC tab|Part number|74x3000 – 74x3999}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x3004
| 1
| selectable [[Gunning transceiver logic|GTL]] voltage reference
|
| {{unknown|analog}}
| (6)
| [http://www.ti.com/lit/gpn/sn74gtl3004 SN74GTL3004]
|-
| 74x3037
| 4
| 4个 2输入 NAND与非门
|
| driver 30&nbsp;Ω
| 16
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n951 74F3037]
|-
| 74x3038
| 4
| 4个 2输入 NAND与非门
|
| open-collector driver 30&nbsp;Ω
| 16
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n955 74F3038]
|-
| 74x3040
| 2
| 2个 4输入 NAND与非门
|
| driver 30&nbsp;Ω
| 16
| [https://archive.org/details/bitsavers_signeticsdaManual_57966640/page/n959 74F3040]
|-
| 74x3125
| 4
| 4个 FET bus switch, output enable active low
|
| {{Unknown|{{sp}}}}
| (14)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n45 SN74CBT3125]
|-
| 74x3126
| 4
| 4个 FET bus switch, output enable active high
|
| {{Unknown|{{sp}}}}
| (14)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n49 SN74CBT3126]
|-
| 74FCT3244
| 2
| 2个 4-bit buffer / line driver
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n509 IDT74FCT3244]
|-
| 74CBT3244,<br/> 74FST3244
| 2
| 2个 4-bit FET bus switch
|
| {{Unknown|{{sp}}}}
| 20
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n53 SN74CBT3244]<br /> [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n641 IDT74FST3244]
|-
| 74FCT3245
| 1
| 8个 bidirectional transceiver
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n515 IDT74FCT3245]
|-
| 74CBT3245,<br /> 74FST3245
| 1
| 8个 FET bus switch
|
| {{Unknown|{{sp}}}}
| 20
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n61 SN74CBT3245A]<br/> [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n645 IDT74FST3245]
|-
| 74LVX3245
| 1
| 8个 bidirectional voltage-translating transceiver
|
| 三态逻辑
| (24)
| [https://archive.org/details/bitsavers_nationaldaCROSSVOLTLowVoltageLogicSeriesDatabook_18426235/page/n129 74LVX3245]
|-
| 74x3251
| 1
| 8-line to 1-line FET multiplexer / demultiplexer
|
| {{Unknown|{{sp}}}}
| (16)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n69 SN74CBT3251]
|-
| 74x3253
| 2
| 2个 4-line to 1-line FET multiplexer / demultiplexer
|
| {{Unknown|{{sp}}}}
| (16)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n73 SN74CBT3253]
|-
| 74x3257
| 4
| 4个 2-line to 1-line FET multiplexer / demultiplexer
|
| {{Unknown|{{sp}}}}
| (16)
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n651 IDT74FST3257]
|-
| 74x3283
| 1
| 32-bit latchable transceiver with parity checker / generator
|
| 三态逻辑
| (120)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-22/DSA-420818.pdf 74ACTQ3283]
|-
| 74x3284
| 1
| 18-bit synchronous datapath multiplexer
|
| 三态逻辑
| (100)
| [https://datasheet.datasheetarchive.com/originals/library/Datasheet-019/DSA00332573.pdf 74ABT3284]
|-
| 74x3305
| 2
| 2个 FET bus switch with extended voltage range
|
| {{Unknown|{{sp}}}}
| (8)
| [https://www.ti.com/lit/gpn/sn74cbt3305c SN74CBT3305C]
|-
| 74x3306
| 2
| 2个 FET bus switch
|
| {{Unknown|{{sp}}}}
| (8)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n85 SN74CBT3306]
|-
| 74x3345
| 1
| 8个 FET bus switch, 2个 output enable
|
| {{Unknown|{{sp}}}}
| (20)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n89 SN74CBT3345]
|-
| 74x3374
| 1
| 8-bit metastable-resistant D-type flip-flop
|
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00215569.pdf SN74AS3374]
|-
| 74x3383
| 1
| 5-bit 4-port FET bus exchange switch
|
| {{Unknown|{{sp}}}}
| 24
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n655 IDT74FST3383]
|-
| 74x3384
| 2
| 2个 5-bit FET bus switch
|
| {{Unknown|{{sp}}}}
| 24
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n509 IDT74FST3384]
|-
| 74x3386
| 1
| 5-bit 4-port FET bus exchange switch with extended voltage range
|
| {{Unknown|{{sp}}}}
| (24)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n113 SN74CBT3386]
|-
| 74x3390
| 1
| 8个 2-line to 1-line FET multiplexer / bus switch
|
| {{Unknown|{{sp}}}}
| (28)
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n665 IDT74FST3390]
|-
| 74x3573
| 1
| 8个 transparent latch
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n521 IDT74FCT3573]
|-
| 74x3574
| 1
| 8个 D-type flip flop
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n527 IDT74FCT3574]
|-
| 74x3584
| 2
| 2个 5-bit FET bus switch
|
| {{Unknown|25&nbsp;Ω series resistor}}
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0025436.pdf QS74QST3584]
|-
| 74x3611
| 1
| 2304-bit FIFO memory (64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n361 SN74ABT3611]
|-
| 74x3612
| 1
| 4608-bit bidirectional FIFO memory (2x64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n387 SN74ABT3612]
|-
| 74x3613
| 1
| 2304-bit FIFO memory (64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n287 SN74ABT3613]
|-
| 74x3614
| 1
| 4608-bit bidirectional FIFO memory (2x64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n319 SN74ABT3614]
|-
| 74x3622
| 1
| 18432-bit bidirectional FIFO memory (2x256x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n177 SN74ACT3622]
|-
| 74x3631
| 1
| 18432-bit FIFO memory (512x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n105 SN74ACT3631]
|-
| 74x3632
| 1
| 36864-bit bidirectional FIFO memory (2x512x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n233 SN74ACT3632]
|-
| 74x3638
| 1
| 32768-bit bidirectional FIFO memory (2x512x32)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n203 SN74ACT3638]
|-
| 74x3641
| 1
| 36864-bit FIFO memory (1024x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n129 SN74ACT3641]
|-
| 74x3642
| 1
| 73728-bit bidirectional FIFO memory (2x1024x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n259 SN74ACT3642]
|-
| 74x3651
| 1
| 73728-bit FIFO memory (2048x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n153 SN74ACT3651]
|-
| 74x3708
| 1
| 8192-bit PROM (1024x8)
|
| open-collector
| 24
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/n177 SN74S3708]
|-
| 74x3807
| 1
| 1-to-10 clock driver
|
| driver
| 20
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n589 IDT74FCT3807]
|-
| 74x3827
| 1
| 10-bit buffer
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n535 IDT74FCT3827]
|-
| 74x3861
| 1
| 10-bit FET bus switch
|
| {{Unknown|{{sp}}}}
| (24)
| [https://archive.org/details/TexasInstruments-TI-Data-CBT5-VandCBTLV3.3-VBusSwitches1998OCR/page/n121 SN74CBT3861]
|-
| 74x3862
| 1
| 10-bit FET bus switch with 2个 output enable
|
| {{Unknown|{{sp}}}}
| (24)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-14/DSA-272858.pdf IDT74CBTLV3862]
|-
| 74x3893
| 1
| 4个 [[Futurebus]] backplane transceiver
|
| 三态逻辑 and open-collector
| (20)
| [https://archive.org/details/bitsavers_motoroladaFASTandLSTTLData_35934218/page/n313 MC74F3893A]
|-
| 74x3907
| 1
| [[P5 (microarchitecture)|Pentium]] clock synthesizer
|
| 三态逻辑
| (28)
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n629 IDT74FCT3907]
|-
| 74x3932
| 1
| PLL-based clock driver
|
| 三态逻辑
| (48)
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n619 IDT74FCT3932]
|-
! {{TOC tab|Part number|74x4000 – 74x5999}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x4002
| 2
| 2个 4输入 NOR 或非门
|
|
| 14
| [https://web.archive.org/web/20170221111335/http://www.ti.com/lit/ds/symlink/cd74hc4002.pdf CD74HC4002]
|-
| 74x4015
| 2
| 2个 4-bit shift registers
|
|
| 16
| [https://web.archive.org/web/20170805221247/http://www.ti.com/lit/ds/symlink/cd74hc4015.pdf CD74HC4015]
|-
| 74x4016
| 4
| 4个 bilateral switch
|
| analog
| 14
| [https://web.archive.org/web/20170305192102/http://www.ti.com/lit/ds/symlink/cd74hc4016.pdf CD74HC4016]
|-
| 74x4017
| 1
| 5-stage ÷10 Johnson counter
|
|
| 16
| [https://web.archive.org/web/20131111151724/http://www.ti.com/lit/ds/symlink/cd74hc4017.pdf CD74HC4017]
|-
| 74x4020
| 1
| 14-stage binary counter
|
|
| 16
| [https://web.archive.org/web/20170305220915/http://www.ti.com/lit/ds/symlink/sn74hc4020.pdf SN74HC4020]
|-
| 74x4022
| 1
| 4-stage ÷8 Johnson counter
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n611 SN74HC4022]
|-
| 74x4024
| 1
| 7-stage ripple carry binary counter
|
|
| 14
| [https://web.archive.org/web/20170305193812/http://www.ti.com/lit/ds/symlink/cd74hc4024.pdf CD74HC4024]
|-
| 74x4028
| 1
| BCD to decimal decoder
|
|
| 16
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00204191.pdf TC74HC4028P]
|-
| 74x4040
| 1
| 12-stage binary ripple counter
|
|
| 16
| [https://web.archive.org/web/20161104125848/http://www.ti.com/lit/ds/symlink/sn74hc4040.pdf SN74HC4040]
|-
| 74x4046
| 1
| [[phase-locked loop]] and [[voltage-controlled oscillator]]
|
|
| 16
| [https://web.archive.org/web/20161130143815/http://www.ti.com/lit/ds/symlink/cd74hc4046a.pdf CD74HC4046A]
|-
| 74x4049
| 6
| 6个 inverting buffer
|
|
| 16
| [https://web.archive.org/web/20170517050814/http://www.ti.com/lit/ds/symlink/cd74hc4050.pdf CD74HC4049]
|-
| 74x4050
| 6
| 6个 buffer/converter (non-inverting)
|
|
| 16
| [https://web.archive.org/web/20170517050814/http://www.ti.com/lit/ds/symlink/cd74hc4050.pdf CD74HC4050]
|-
| 74x4051
| 1
| high-speed 8-channel analog multiplexer/demultiplexer
|
| analog
| 16
| [https://web.archive.org/web/20161213211740/http://www.ti.com/lit/ds/symlink/cd74hc4051.pdf CD74HC4051]
|-
| 74x4052
| 2
| 2个 4-channel analog multiplexer/demultiplexers
|
| analog
| 16
| [https://web.archive.org/web/20161213211740/http://www.ti.com/lit/ds/symlink/cd74hc4051.pdf CD74HC4052]
|-
| 74x4053
| 3
| 3个 2-channel analog multiplexer/demultiplexers
|
| analog
| 16
| [https://web.archive.org/web/20161213211740/http://www.ti.com/lit/ds/symlink/cd74hc4051.pdf CD74HC4053]
|-
| 74x4059
| 1
| programmable divide-by-N counter
|
|
| 24
| [https://web.archive.org/web/20161104185610/http://www.ti.com/lit/ds/symlink/cd74hc4059.pdf CD74HC4059]
|-
| 74x4060
| 1
| 14-stage binary ripple counter with oscillator
|
|
| 16
| [https://web.archive.org/web/20170306011107/http://www.ti.com/lit/ds/symlink/sn74hc4060.pdf SN74HC4060]
|-
| 74x4061
| 1
| 14-stage asynchronous binary counter with oscillator
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n449 SN74HC4061]
|-
| 74x4066
| 4
| 4个 single-pole single-throw analog switch
|
|
| 14
| [https://web.archive.org/web/20170305221555/http://www.ti.com/lit/ds/symlink/sn74hc4066.pdf SN74HC4066]
|-
| 74x4067
| 1
| 16-channel analog multiplexer/demultiplexer
|
| analog
| 24
| [https://web.archive.org/web/20170804052235/http://www.ti.com/lit/ds/symlink/cd74hc4067.pdf CD74HC4067]
|-
| 74x4072
| 2
| 2个 4输入  OR或门
|
|
| 14
| [http://www.htmldatasheet.com/pdf/toshiba/tc74hc4072.pdf TC74HC4072]
|-
| 74x4075
| 3
| 3个 3输入  OR或门
|
|
| 14
| [http://www.ti.com/lit/gpn/CD74HCT4075 CD74HC4075]
|-
| 74x4078
| 1
| 1个 8输入 OR或门/NOR 或非门
|
|
| 14
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n701 MM74HC4078]
|-
| 74x4094
| 1
| 8-bit three-state shift register/latch
|
| 三态逻辑
| 16
| [https://web.archive.org/web/20170706105747/http://www.ti.com/lit/ds/symlink/cd74hc4094.pdf CD74HC4094]
|-
| 74x4102
| 1
| 2-digit BCD presettable synchronous down counter
|
|
| 16
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-055/DSAIH000112054.pdf 74HC4202]
|-
| 74x4103
| 1
| 8-bit binary presettable synchronous down counter
|
|
| 16
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-055/DSAIH000112054.pdf 74HC4203]
|-
| 74x4245
| 1
| 8-bit 3V/5V translating transceiver
|
| 三态逻辑
| (24)
| [https://archive.org/details/bitsavers_nationaldaCROSSVOLTLowVoltageLogicSeriesDatabook_18426235/page/n135 74LVX4245]
|-
| 74x4301
| 1
| 8-bit latch, inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n413 MN74HC4301]
|-
| 74x4302
| 1
| 8-bit latch, non-inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n417 MN74HC4302]
|-
| 74x4303
| 1
| 8-bit D-type flip-flop, inverting outputs
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n421 MN74HC4303]
|-
| 74x4304
| 1
| 8-bit D-type flip-flop, non-inverting outputs
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n425 MN74HC4304]
|-
| 74x4305
| 2
| 2个 4-bit buffer, inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n429 MN74HC4305]
|-
| 74x4306
| 2
| 2个 4-bit buffer, non-inverting
|
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_panasonicdicHighSpeedCMOS_23161100/page/n433 MN74HC4306]
|-
| 74x4316
| 4
| 4个 analog switch
|
| analog
| 14
| [https://archive.org/details/bitsavers_nationaldaLogicDatabookVolume1_95500749/page/nal_Logic_Databook_Volume_1#page/n703 MM74HC4316]
|-
| 74x4351
| 1
| 8-channel analog multiplexer/demultiplexer with latch
|
| analog
| 20
| [http://www.ti.com/lit/gpn/cd74hc4352 CD74HC4351]
|-
| 74x4352
| 2
| 2个 4-channel analog multiplexer/demultiplexer with latch
|
| analog
| 20
| [http://www.ti.com/lit/gpn/cd74hc4352 CD74HC4352]
|-
| 74x4353
| 3
| 3个 2-channel  analog multiplexer/demultiplexer with latch
|
| analog
| 20
| [https://archive.org/details/bitsavers_motoroladaHighSpeedCMOSData_40597139/page/n741 MC74HC4353]
|-
| 74x4374
| 1
| 8-bit 2个-rank synchronizer
|
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-056/DSAIH000137795.pdf SN74AS4374]
|-
| 74x4503
| 1
| controller for 64k/256k/1M dynamic RAM
|
| 三态逻辑
| 52
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ACT4503]
|-
| 74x4510
| 1
| BCD decade up/down counter
|
|
| 16
| [https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n559 CD74HC4510]
|-
| 74x4511
| 1
| BCD to 7-segment decoder
|
|
| 16
| [http://www.ti.com/lit/gpn/cd54hc4511 CD74HC4511]
|-
| 74x4514
| 1
| 4-to-16 line decoder/demultiplexer, input latches
|
|
| 24
| [http://www.ti.com/lit/gpn/cd54hc4514 CD74HC4514]
|-
| 74x4515
| 1
| 4-to-16 line decoder/demultiplexer with input latches; inverting
|
|
| 24
| [http://www.ti.com/lit/gpn/cd54hc4514 CD74HC4515]
|-
| 74x4516
| 1
| 4-bit binary up/down counter
|
|
| 16
| [https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n559 CD74HC4516]
|-
| 74x4518
| 2
| 2个 4-bit synchronous decade counter
|
|
| 16
| [http://www.ti.com/lit/gpn/cd74hc4520 CD74HC4518]
|-
| 74x4520
| 2
| 2个 4-bit synchronous binary counter
|
|
| 16
| [http://www.ti.com/lit/gpn/cd74hc4520 CD74HC4520]
|-
| 74x4538
| 2
| 2个 retriggerable precision monostable multivibrator
|
|
| 16
| [http://www.ti.com/lit/gpn/cd54hc4538 CD74HC4538]
|-
| 74x4543
| 1
| BCD to 7-segment latch/decoder/driver for LCDs
|
|
| 16
| [http://www.ti.com/lit/gpn/cd74hc4543 CD74HC4543]
|-
| 74x4560
| 1
| 4-bit BCD adder
|
|
| 16
| [https://archive.org/details/bitsavers_nationalda74HCDatabook_36362852/page/n531 MM74HC4560]
|-
| 74x4724
| 1
| 8-bit addressable latch
|
|
| 16
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n457 SN74HC4724]
|-
| 74x4764
| 1
| programmable dRAM controller
|
|
| (100)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-110/DSAP0018785.pdf 74ABT4764]
|-
| 74x4799
| 1
| Timer for NiCd and NiMH chargers
| Schmitt trigger
| open-collector and three-state
| 16
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-25/DSA-494778.pdf 74LV4799]
|-
| 74x4851
| 1
| 8-channel analog multiplexer/demultiplexer
|
| analog
| 16
| [https://web.archive.org/web/20160508140402/http://www.ti.com/lit/ds/symlink/sn74hc4851.pdf SN74HC4851]
|-
| 74x4852
| 2
| 2个 4-channel analog multiplexer/demultiplexer
|
| analog
| 16
| [http://www.ti.com/lit/gpn/sn74hc4852 SN74HC4852]
|-
| 74x5074
| 2
| 2个 positive edge-triggered D-type flip-flop (metastable immune)
|
|
| 14
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-25/DSA-496118.pdf 74ABT5074]
|-
| 74x5245
| 1
| 8个 bidirectional transceiver
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n417 DM74ALS5245]
|-
| 74x5300
| 1
| fiber optic LED driver
|
| driver 120&nbsp;mA
| 8
| [http://pdf.datasheetcatalog.com/datasheet/philips/N74F5300D.pdf 74F5300]
|-
| 74x5302
| 2
| 2个 fiber optic LED / clock driver
|
| driver 160&nbsp;mA
| 14
| [http://www.datasheetbank.com/datasheet-download/530792/1/Philips/74F5302 74F5302]
|-
| 74x5400
| 1
| 11-bit line/memory driver, non-inverting
|
| 三态逻辑, 25 Ω series resistor
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n605 SN74ABT5400]
|-
| 74x5401
| 1
| 11-bit line/memory driver, inverting
|
| 三态逻辑, 25 Ω series resistor
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n609 SN74ABT5401]
|-
| 74x5402
| 1
| 12-bit line/memory driver, non-inverting
|
| 三态逻辑, 25 Ω series resistor
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n613 SN74ABT5402]
|-
| 74x5403
| 1
| 12-bit line/memory driver, inverting
|
| 三态逻辑, 25 Ω series resistor
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n617 SN74ABT5403]
|-
| 74x5555
| 1
| programmable delay timer with oscillator
|
|
| 16
| [https://assets.nexperia.com/documents/data-sheet/74HC5555.pdf 74HC5555]
|-
| 74x5620
| 1
| 8个 bidirectional transceiver
| Schmitt trigger
| 三态逻辑
| 20
| [https://archive.org/details/bitsavers_nationaldaicDatabook_22808448/page/n417 DM74ALS5620]
|-
! {{TOC tab|Part number|74x6000 and above}}
! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x6000
| 1
| logic-to-logic optocoupler, non-inverting
|
|
| 6
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-12/DSA-229129.pdf 74OL6000]
|-
| 74x6001
| 1
| logic-to-logic optocoupler, inverting
|
|
| 6
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-12/DSA-229129.pdf 74OL6001]
|-
| 74x6010
| 1
| logic-to-logic optocoupler, non-inverting
|
| open-collector 15&nbsp;V
| 6
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-12/DSA-229129.pdf 74OL6010]
|-
| 74x6011
| 1
| logic-to-logic optocoupler, inverting
|
| open-collector 15&nbsp;V
| 6
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-12/DSA-229129.pdf 74OL6011]
|-
| 74x6300
| 1
| programmable dynamic memory refresh timer
|
|
| 16
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ALS6300]
|-
| 74x6301
| 1
| dynamic memory refresh controller, transparent and burst modes, for 16K, 64K, 256K, and 1M dRAM
|
|
| 52
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n535 SN74ALS6301]
|-
| 74x6302
| 1
| dynamic memory refresh controller, transparent and burst modes, for 16K, 64K, 256K, and 1M dRAM
|
|
| 52
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n535 SN74ALS6302]
|-
| 74x6310
| 1
| static column and page mode access detector for dRAM
|
|
| 20
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ALS6310A]
|-
| 74x6311
| 1
| static column and page mode access detector for dRAM
|
|
| 20
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74ALS6311A]
|-
| 74x6323
| 1
| programmable ripple counter with oscillator
|
| 三态逻辑
| (8)
| [https://assets.nexperia.com/documents/data-sheet/74HC_HCT6323A.pdf 74HC6323A]
|-
| 74x6364
| 1
| 64-bit flow-through error detection and correction circuit
|
| 三态逻辑
| (207)
| [https://usermanual.wiki/Document/1990TICacheMemoryManagementDataBook.1210032352.pdf SN74AS6364]
|-
| 74x6800
| 1
| 10-bit FET bus switch with precharge
|
| {{unknown|{{sp}}}}
| 24
| [https://archive.org/details/bitsavers_idtdataBoomanceLogicDataBook_51362967/page/n671 IDT74FST6800]
|-
| 74x6845
| 1
| 8-bit FET bus switch with precharge and extended voltage range
|
| {{unknown|{{sp}}}}
| (20)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-711566.pdf SN74CBT6845C]
|-
| 74x7001
| 4
| 4个 2输入 AND与门
| Schmitt trigger
|
| 14
| [http://www.ti.com/lit/gpn/sn74hc7001 SN74HC7001]
|-
| 74x7002
| 4
| 4个 2输入 NOR 或非门
| Schmitt trigger
|
| 14
| [http://www.ti.com/lit/gpn/sn74hc7002 SN74HC7002]
|-
| 74x7003
| 4
| 4个 2输入 NAND与非门
| Schmitt trigger
| open-collector
| 14
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n707 SN74HC7003]
|-
| 74x7006
| 6
| two inverters, one 3输入 NAND, one 4输入 NAND, one 3输入 NOR, one 4输入 NOR
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookSLogicDataBook_45157566/page/n773 SN74HC7006]
|-
| 74x7007
| 6
| 6个 buffer gate
|
|
| 14
| [https://www.alldatasheet.com/datasheet-pdf/pdf/31796/TOSHIBA/TC74HCT7007AF.html TC74HCT7007AP]
|-
| 74x7008
| 6
| two inverters, three 2输入 NAND, three 2输入 NOR
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookSLogicDataBook_45157566/page/n777 SN74HC7008]
|-
| 74x7014
| 6
| 6个 buffer gate
| Schmitt trigger
|
| 14
| [https://assets.nexperia.com/documents/data-sheet/74HC7014.pdf 74HC7014]
|-
| 74x7022
| 1
| 4-stage ÷8 Johnson counter with power-up clear
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n615 SN74HC7022]
|-
| 74x7030
| 1
| 576-bit FIFO memory (64x9)
|
| 三态逻辑
| 28
| [https://archive.org/details/highspeedcmosda00sign/page/764 74HC7030]
|-
| 74x7032
| 4
| 4个 2输入  OR或门s
| Schmitt trigger
|
| 14
| [https://archive.org/details/bitsavers_tidataBookSLogicDataBook_45157566/page/n787 SN74HC7032]
|-
| 74x7038
| 1
| 9-bit bus transceiver with latch
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n641 CD74HC7038]
|-
| 74x7046
| 1
| [[phase-locked loop]] with [[voltage-controlled oscillator]] and lock detector
|
|
| 16
| [http://www.ti.com/lit/gpn/cd74hc7046a CD74HC7046A]
|-
| 74x7060
| 1
| 14-stage binary counter with oscillator
| Schmitt trigger
|
| 20
| [https://archive.org/details/RCA-RCAAdvancedCMOSLogicICs1987OCR/page/n291 CD74AC7060]
|-
| 74x7074
| 6
| two inverters, one 2输入 NAND, one 2输入 NOR, two D-type flip-flops
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookSLogicDataBook_45157566/page/n791 SN74HC7074]
|-
| 74x7075
| 6
| two inverters, two 2输入 NAND, two D-type flip-flops
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookSLogicDataBook_45157566/page/n797 SN74HC7075]
|-
| 74x7076
| 6
| two inverters, two 2输入 NOR, two D-type flip-flops
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookSLogicDataBook_45157566/page/n803 SN74HC7076]
|-
| 74x7080
| 1
| 16-bit parity generator / checker
|
|
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-25/DSA-491964.pdf 74HCT7080]
|-
| 74x7132
| 4
| 4个 adjustable comparator with output latches
| Schmitt trigger
| 三态逻辑
| 14
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-30/DSA-596949.pdf 74HCT7132]
|-
| 74x7200
| 1
| 2304-bit FIFO memory (256x9)
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n695 SN74ACT7200L]
|-
| 74x7201
| 1
| 4608-bit FIFO memory (512x9)
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n695 SN74ACT7201LA]
|-
| 74x7202
| 1
| 9216-bit FIFO memory (1024x9)
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n695 SN74ACT7202LA]
|-
| 74x7203
| 1
| 18432-bit FIFO memory (2048x9)
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n715 SN74ACT7203L]
|-
| 74ACT7204
| 1
| 36864-bit FIFO memory (4096x9)
|
|
| 28
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n715 SN74ACT7204L]
|-
| 74HCU7204
| 2
| 2个 unbuffered inverters
|
|
| (8)
| [http://www.ti.com/lit/gpn/sn74hcu7204 SN74HCU7204]
|-
| 74x7205
| 1
| 73728-bit FIFO memory (8192x9)
|
|
| 28
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-705735.pdf SN74ACT7205L]
|-
| 74x7206
| 1
| 147456-bit FIFO memory (16384x9)
|
|
| 28
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-36/DSA-705735.pdf SN74ACT7206L]
|-
| 74x7240
| 1
| 8个 bus buffer, inverting
| Schmitt trigger
| 三态逻辑
| 20
| [http://pdf.datasheet.live/datasheets-1/toshiba/TC74HC7241AP.pdf TC74HC7240AP]
|-
| 74x7241
| 1
| 8个 bus buffer, non-inverting
| Schmitt trigger
| 三态逻辑
| 20
| [http://pdf.datasheet.live/datasheets-1/toshiba/TC74HC7241AP.pdf TC74HC7241AP]
|-
| 74x7244
| 1
| 8个 bus buffer, non-inverting
| Schmitt trigger
| 三态逻辑
| 20
| [http://pdf.datasheet.live/datasheets-1/toshiba/TC74HC7241AP.pdf TC74HC7244AP]
|-
| 74x7245
| 1
| 8个 bus transceiver, non-inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7245]
|-
| 74x7266
| 4
| 4个 2输入 XNOR异或非门
|
|
| 14
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n461 SN74HC7266]
|-
| 74x7273
| 8
| 8个 positive edge-triggered D-type flip-flop with reset
|
| open-collector
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-25/DSA-496043.pdf 74HCT7273]
|-
| 74x7292
| 1
| programmable divider/timer
|
|
| 16
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/31771/TOSHIBA/TC74HC7292AP.html TC74HC7292AP]
|-
| 74x7294
| 1
| programmable divider/timer
|
|
| 16
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/23075/STMICROELECTRONICS/M74HC7294.html M74HC7294]
|-
| 74x7340
| 1
| 8-bit bus driver with bidirectional registers
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookogicDataBook_23574286/page/n625 SN74HC7340]
|-
| 74x7403
| 1
| 256-bit FIFO memory (64x4)
|
| 三态逻辑
| 16
| [http://pdf.datasheetcatalog.com/datasheet/philips/74HC7403.pdf 74HC7403]
|-
| 74x7404
| 1
| 320-bit FIFO memory (64x5)
|
| 三态逻辑
| 18
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/15661/PHILIPS/74HC7404.html 74HC7404]
|-
| 74x7540
| 8
| 8个 buffer/line driver, inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://assets.nexperia.com/documents/data-sheet/74HC_HCT7540.pdf 74HC7540]
|-
| 74x7541
| 8
| 8个 buffer/line driver, non-inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://assets.nexperia.com/documents/data-sheet/74HC_HCT7541.pdf 74HC7541]
|-
| 74x7597
| 1
| 8-bit shift register with input latches
|
|
| 16
| [http://pdf.datasheetcatalog.com/datasheet/philips/74HC7597.pdf 74HC7597]
|-
| 74x7623
| 1
| 8个 bus transceiver, non-inverting
|
| 三态逻辑 and open-drain
| 20
| [https://archive.org/details/RCA-RCAAdvancedCMOSLogicICs1987OCR/page/n293 CD74AC7623]
|-
| 74x7640
| 1
| 8个 bus transceiver, inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7640]
|-
| 74x7643
| 1
| 8个 bus transceiver, non-inverting/inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7643]
|-
| 74x7645
| 1
| 8个 bus transceiver, non-inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://pdf1.alldatasheet.com/datasheet-pdf/view/23130/STMICROELECTRONICS/M74HC7645.html M74HC7645]
|-
| 74x7731
| 4
| 4个 64-bit static shift register
|
|
| 16
| [http://pdf.datasheetcatalog.com/datasheet/philips/74HCT7731.pdf 74HC7731]
|-
| 74x7793
| 1
| 8-bit noninverting transparent latch with readback
|
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0048904.pdf MC74HC7793]
|-
| 74x7801
| 1
| 18432-bit FIFO memory (1024x18), clocked
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n21 SN74ACT7801]
|-
| 74x7802
| 1
| 18432-bit FIFO memory (1024x18)
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n115 SN74ACT7802]
|-
| 74x7803
| 1
| 9216-bit FIFO memory (512x18), clocked
|
| 三态逻辑
| (56)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n37 SN74ACT7803]
|-
| 74x7804
| 1
| 9216-bit FIFO memory (512x18)
|
| 三态逻辑
| (56)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n127 SN74ACT7804]
|-
| 74x7805
| 1
| 4608-bit FIFO memory (256x18), clocked
|
| 三态逻辑
| (56)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n51 SN74ACT7805]
|-
| 74x7806
| 1
| 4608-bit FIFO memory (256x18)
|
| 三态逻辑
| (56)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n139 SN74ACT7806]
|-
| 74x7807
| 1
| 18432-bit FIFO memory (2048x9), clocked
|
| 三态逻辑
| (44)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n65 SN74ACT7807]
|-
| 74x7808
| 1
| 18432-bit FIFO memory (2048x9)
|
| 三态逻辑
| (44)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n151 SN74ACT7808]
|-
| 74x7811
| 1
| 18432-bit FIFO memory (1024x18), clocked
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n81 SN74ACT7811]
|-
| 74x7813
| 1
| 1152-bit FIFO memory (64x18), clocked
|
| 三态逻辑
| (56)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n99 SN74ACT7813]
|-
| 74x7814
| 1
| 1152-bit FIFO memory (64x18)
|
| 三态逻辑
| (56)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n165 SN74ACT7814]
|-
| 74x7815
| 1
| 4608-bit bidirectional FIFO memory(2x64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n279 SN74ABT7815]
|-
| 74x7816
| 1
| 4608-bit bidirectional FIFO memory(2x64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n291 SN74ABT7816]
|-
| 74x7817
| 1
| 2304-bit FIFO memory(64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n293 SN74ABT7817]
|-
| 74x7818
| 1
| 2304-bit FIFO memory(64x36)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n295 SN74ABT7818]
|-
| 74x7819
| 1
| 18432-bit bidirectional FIFO memory (2x512x18), clocked
|
| 三态逻辑
| (80)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n207 SN74ABT7819]
|-
| 74x7820
| 1
| 18432-bit bidirectional FIFO memory (2x512x18)
|
| 三态逻辑
| (80)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n229 SN74ABT7820]
|-
| 74x7821
| 1
| 32768-bit bidirectional FIFO memory (2x512x32)
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n317 SN74ACT7821]
|-
| 74x7822
| 1
| 32768-bit bidirectional FIFO memory (2x512x32), clocked
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n325 SN74ACT7822]
|-
| 74x7823
| 1
| 36864-bit FIFO memory (1024x36), clocked
|
| 三态逻辑
| (120)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook400_13134187/page/n333 SN74ACT7823]
|-
| 74x7881
| 1
| 18432-bit FIFO memory (1024x18), clocked
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n479 SN74ACT7881]
|-
| 74x7882
| 1
| 36864-bit FIFO memory (2048x18), clocked
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n495 SN74ACT7882]
|-
| 74x7884
| 1
| 73728-bit FIFO memory (4096x18), clocked
|
| 三态逻辑
| (68)
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDataBook_33517703/page/n511 SN74ACT7884]
|-
| 74x8003
| 2
| 2个 2输入 NAND与非门
|
|
| 8
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n771 SN74ALS8003]
|-
| 74x8151
| 1
| 10-bit inverting/non-inverting buffer
| Schmitt trigger
| 三态逻辑
| 24
| [http://www.ti.com/lit/gpn/sn74lv8151 SN74LV8151]
|-
| 74x8153
| 1
| 8-bit serial-to-parallel interface
|
| 三态逻辑 or open-collector
| 20
| [http://www.ti.com/lit/gpn/sn74lv8153 SN74LV8153]
|-
| 74x8154
| 2
| 2个 16-bit counters with output registers
|
| 三态逻辑
| 20
| [http://www.ti.com/lit/gpn/sn74lv8154 SN74LV8154]
|-
| 74x8161
| 1
| 8-bit synchronous binary counter
|
|
| 24
| [https://datasheet.datasheetarchive.com/originals/scans/Scans-067/DSA2IH00215541.pdf SN74ALS8161]
|-
| 74x8240
| 1
| 8个 inverting buffer with [[JTAG]] port
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n23 SN74BCT8240A]
|-
| 74x8244
| 1
| 8个 non-inverting buffer with [[JTAG]] port
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n43 SN74BCT8244A]
|-
| 74x8245
| 1
| 8个 bus transceiver with [[JTAG]] port
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n735 SN74ABT8245]
|-
| 74x8373
| 1
| 8个 D-type latch with [[JTAG]] port
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n85 SN74BCT8373A]
|-
| 74x8374
| 1
| 8个 D-type edge-triggered flip-flop with [[JTAG]] port
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n105 SN74BCT8374A]
|-
| 74x8400
| 1
| expandable error checker / corrector
|
| 三态逻辑
| 48
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n541 SN74ALS8400]
|-
| 74x8541
| 1
| 8-bit buffer, selectable inverting/non-inverting
| Schmitt trigger
| 三态逻辑
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/DKDS41/DSANUWW0029467.pdf SN74AHC8541]
|-
| 74x8543
| 1
| 8个 registered bus transceiver with [[JTAG]] port
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n757 SN74ABT8543]
|-
| 74x8646
| 1
| 8个 bus transceiver and register with [[JTAG]] port
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n765 SN74ABT8646]
|-
| 74x8652
| 1
| 8个 bus transceiver and register with [[JTAG]] port
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n775 SN74ABT8652]
|-
| 74x8818
| 1
| 16-bit microprogram sequencer, cascadable
|
| 三态逻辑
| (84)
| [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n19 SN74ACT8818]
|-
| 74x8832
| 1
| 32-bit registered ALU
|
| 三态逻辑
| (208)
| [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n79 SN74ACT8832]
|-
| 74x8834
| 1
| 40-bit register file
|
| 三态逻辑
| (156)
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n545 SN74AS8834]
|-
| 74x8835
| 1
| 16-bit microprogram sequencer, cascadable
|
| 三态逻辑
| (156)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0053260.pdf SN74AS8835]
|-
| 74x8836
| 1
| 32x32-bit multiplier/accumulator
|
| 三态逻辑
| (156)
| [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n273 SN74ACT8836]
|-
| 74x8837
| 1
| 64-bit floating point unit
|
| 三态逻辑
| (208)
| [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n307 SN74ACT8837]
|-
| 74x8838
| 1
| 64-bit barrel shifter
|
| 三态逻辑
| (84)
| [https://archive.org/details/bitsavers_tidataBook_28346484/page/n555 SN74AS8838]
|-
| 74x8839
| 1
| 32-bit shuffle/exchange network
|
| 三态逻辑
| (85)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0053259.pdf SN74AS8839]
|-
| 74x8840
| 1
| digital crossbar switch
|
| 三态逻辑
| (156)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-110/DSAP0010220.pdf SN74AS8840]
|-
| 74x8841
| 1
| digital crossbar switch
|
| 三态逻辑
| (156)
| [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n435 SN74ACT8841]
|-
| 74x8847
| 1
| 64-bit floating point and integer unit
|
| 三态逻辑
| (208)
| [https://archive.org/details/bitsavers_tidataBookamily32BitCMOSProcessorBuildingBlocksDat_39357329/page/n461 SN74ACT8847]
|-
| 74x8867
| 1
| 32-bit vector processor unit
|
| 三态逻辑
| (208)
| [https://archive.org/details/TexasInstruments-TI-Data-SN74ACT8800Family32-BitCMOSProcessorBuildingBlocks1990OCR/page/n495 SN74ACT8867]
|-
| 74x8952
| 1
| 8个 registered bus transceiver with [[JTAG]] port
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookiCMOSTechnologyDataBook_40217042/page/n785 SN74ABT8952]
|-
| 74x8960
| 1
| 8-bit bidirectional latched [[FutureBus]] transceiver, inverting
|
| 三态逻辑 and open-collector
| 28
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8960_PhilipsSemiconductors.pdf 74F8960]
|-
| 74x8961
| 1
| 8-bit bidirectional latched [[FutureBus]] transceiver, non-inverting
|
| 三态逻辑 and open-collector
| 28
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8960_PhilipsSemiconductors.pdf 74F8961]
|-
| 74x8962
| 1
| 9-bit bidirectional latched [[FutureBus]] transceiver, inverting
|
| 三态逻辑 and open-collector
| (44)
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8962_PhilipsSemiconductors.pdf 74F8962]
|-
| 74x8963
| 1
| 9-bit bidirectional latched [[FutureBus]] transceiver, non-inverting
|
| 三态逻辑 and open-collector
| (44)
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8962_PhilipsSemiconductors.pdf 74F8963]
|-
| 74x8965
| 1
| 9-bit bidirectional latched [[FutureBus]] transceiver, latch select
|
| 三态逻辑 and open-collector
| (44)
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8965_PhilipsSemiconductors.pdf 74F8965]
|-
| 74x8966
| 1
| 9-bit bidirectional latched [[FutureBus]] transceiver, idle arbitration request / output
|
| 三态逻辑 and open-collector
| (44)
| [https://cdn.datasheetspdf.com/pdf-down/7/4/F/74F8965_PhilipsSemiconductors.pdf 74F8966]
|-
| 74x8980
| 1
| [[JTAG]] test access port master with 8-bit host interface
|
| 三态逻辑
| 24
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n795 SN74LVT8980]
|-
| 74x8986
| 1
| linkable, multidrop-addressable [[JTAG]] transceiver
|
| 三态逻辑
| (64)
| [http://www.ti.com/lit/gpn/sn74lvt8986 SN74LVT8986]
|-
| 74x8990
| 1
| [[JTAG]] test access port master with 16-bit host interface
|
| 三态逻辑
| (44)
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n825 SN74ACT8990]
|-
| 74x8994
| 1
| [[JTAG]] scan-controlled logic/signature analyzer
|
|
| (28)
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n837 SN74ACT8994]
|-
| 74x8996
| 1
| multidrop-addressable [[JTAG]] transceiver
|
|
| 24
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n847 SN74ABT8996]
|-
| 74x8997
| 1
| scan-controlled [[JTAG]] concatenator
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n887 SN74ACT8997]
|-
| 74x8999
| 1
| scan-controlled [[JTAG]] multiplexer
|
| 三态逻辑
| 28
| [https://archive.org/details/bitsavers_tidataBookLogicDataBook_44713328/page/n911 SN74ACT8999]
|-
| 74x9000
| 1
| programmable timer with oscillator
|
|
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0048905.pdf MC74HC9000]
|-
| 74x9014
| 9
| nine-wide buffer/line driver, inverting
| Schmitt trigger
|
| 20
| [http://pdf.datasheetcatalog.com/datasheet/philips/74HCT9014.pdf 74HC9014]
|-
| 74x9015
| 9
| nine-wide buffer/line driver, non-inverting
| Schmitt trigger
|
| 20
| [http://pdf.datasheetcatalog.com/datasheet/philips/74HC9015.pdf 74HC9015]
|-
| 74x9034
| 9
| nine-wide buffer, inverting
|
|
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0048907.pdf MC74HC9034]
|-
| 74x9035
| 9
| nine-wide buffer, noninverting
|
|
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0048907.pdf MC74HC9035]
|-
| 74x9046
| 1
| PLL with band gap controlled VCO
|
|
| 16
| [https://assets.nexperia.com/documents/data-sheet/74HCT9046A.pdf 74HCT9046]
|-
| 74x9114
| 9
| nine-wide inverter
| Schmitt trigger
| open-collector
| 20
| [https://assets.nexperia.com/documents/data-sheet/74HC_HCT9114.pdf 74HC9114]
|-
| 74x9115
| 9
| nine-wide buffer
| Schmitt trigger
| open-collector
| 20
| [https://assets.nexperia.com/documents/data-sheet/74HC9115.pdf 74HC9115]
|-
| 74x9134
| 9
| nine-wide buffer, inverting
|
| open-collector
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0048910.pdf MC74HC9134]
|-
| 74x9135
| 9
| nine-wide buffer, noninverting
|
| open-collector
| 20
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0048910.pdf MC74HC9135]
|-
| 74x9164
| 1
| 8-bit shift register (serial in/out, parallel in/out)
| Schmitt trigger
| 三态逻辑
| (16)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-SFU3/DSASFU100040800.pdf TC74VHC9164]
|-
| 74x9240
| 1
| 9-bit buffer / line driver, inverting
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-211521.pdf 74FR9240]
|-
| 74x9244
| 1
| 9-bit buffer / line driver, non-inverting
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-212907.pdf 74FR9244]
|-
| 74x9245
| 1
| 9-bit bidirectional transceiver, non-inverting
|
| 三态逻辑
| 24
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-11/DSA-203499.pdf 74FR9245]
|-
| 74x9323
| 1
| programmable ripple counter with oscillator
|
| 三态逻辑
| (8)
| [http://pdf.datasheetcatalog.com/datasheet/philips/74HCT7731.pdf 74HC9323A]
|-
| 74x9510
| 1
| 16×16-bit multiplier/accumulator (compatible to [[List of AMD Am2900 and Am29000 families#Am29500 Family|Am29510]] and [[Digital signal processor#Background|TDC1010]])
|
| 三态逻辑
| (68)
| 74HC9510<ref name=hcmostb/>{{rp|534}}
|-
| 74x9595
| 1
| 8-bit shift register with latch (serial in, parallel out)
| Schmitt trigger
|
| (16)
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-SFU3/DSASFU100040801.pdf TC74VHC9595]
|-
| 74x40102
| 1
| presettable synchronous 2-decade BCD down counter
|
|
| 16
| [https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n603 CD74HC40102]
|-
| 74x40103
| 1
| presettable 8-bit synchronous down counter
|
|
| 16
| [https://web.archive.org/web/20161104125904/http://www.ti.com/lit/ds/symlink/cd74hc40103.pdf CD74HC40103]
|-
| 74x40104
| 4
| 4-bit bidirectional universal shift register
|
| 三态逻辑
| 16
| [https://archive.org/details/bitsavers_rcadataBooMOS_35821859/page/n613 CD74HC40104]
|-
| 74x40105
| 1
| 64-bit FIFO memory (16x4)
|
| 三态逻辑
| 16
| [http://www.ti.com/lit/gpn/cd74hc40105 CD74HC40105]
|-
! 芯片型号 !! 片内门电路个数 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|}
 
==Smaller footprints==
As board designs have migrated away from large amounts of logic chips, so has the need for many of the same gate in one package.  Since about 1996,<ref>{{cite web |title=The Fairchild Division of National Semiconductor Introduces Industry's Fastest 5V Single-Gate Logic |url=http://fairchildsemi.com:80/news/1996/9611/dm96001dl.html |archive-url=https://web.archive.org/web/19980512215641/http://fairchildsemi.com/news/1996/9611/dm96001dl.html |url-status=dead |archive-date=1998-05-12  |publisher=[[Fairchild Semiconductor]] |access-date=July 27, 2018 |date=November 25, 1996 }}</ref> there has been an ongoing trend towards one / two / three logic gates per chip. Now logic can be placed where it is physically needed on a board, instead of running long signal traces to a full-size logic chip that has many of the same gate.<ref>{{cite web |title=Unique and Novel Uses for ON Semiconductor's New One-Gate family |url=http://www.onsemi.com/pub/Collateral/AND8018-D.PDF |publisher=[[ON Semiconductor]] |archive-url=https://web.archive.org/web/20010709003217/http://www.onsemi.com/pub/Collateral/AND8018-D.PDF |archive-date=2001-07-09  |date=June 2000 |url-status=live |access-date=2018-07-27  }}</ref>
 
All chips in the following sections are available 5- to 10-pin [[Surface-mount technology|surface-mount packages]]. The right digits, after the 1G/2G/3G, typically has the same functional features as older legacy chips, except for the multifunctional chips and 4-digit chip numbers, which are unique to these newer families. The "x" in the part number is a place holder for the logic family name. For example, 74x1G14 in "LVC" logic family would be "74LVC1G14". The previously stated prefixes of "SN-" and "MC-" are used to denote manufacturers, Texas Instruments and ON Semiconductor respectively.<ref name="TI-L-LG">[http://www.ti.com/lit/sg/scyt129g/scyt129g.pdf 2018 Little Logic Guide; Texas Instruments].</ref><ref name="NXP-AUP-LG">[https://assets.nexperia.com/documents/brochure/75017458.pdf 74AUP Logic Guide; NXP].</ref><ref name="NXP-LVC-LG">[https://assets.nexperia.com/documents/brochure/75017668.pdf 74LVC Logic Guide; NXP].</ref>
 
Some of the manufacturers that make these smaller IC chips are: [[Diodes Incorporated]], [[Nexperia]] ([[NXP Semiconductors]]), [[ON Semiconductor]] ([[Fairchild Semiconductor]]), [[Texas Instruments]] ([[National Semiconductor]]), [[Toshiba]].
 
The [[7400 series#7400 series derivative families|logic families]] available in small footprints are: AHC, AHCT, AUC, AUP, AXP, HC, HCT, LVC, VHC, NC7S, NC7ST, NC7SU, NC7SV. The LVC family is very popular in small footprints because it supports the most common logic voltages of 1.8&nbsp;V, 3.3&nbsp;V, 5&nbsp;V, its inputs are 5&nbsp;V tolerant when the device is powered at a lower voltage, and an output drive of 24&nbsp;mA. Gates that are commonly available across most small footprint families are 00, 02, 04, 08, 14, 32, 86, 125, 126.
 
===One-gate chips===
All chips in this section have one gate, noted by the "1G" in the part numbers.
 
{|class="wikitable sortable"
! 芯片型号 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x1G00
| 1个 2输入 [[与非门]]
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G00.pdf LVC]
|-
| 74x1G02
| 1个 2输入 [[NOR 或非门]]
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G02.pdf LVC]
|-
| 74x1G04
| 1个 [[非门]]
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G04.pdf LVC]
|-
| 74x1G06
| 1个 非门
| [[schmitt trigger]]
| [[Open drain|open-drain]]
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G06.pdf LVC]
|-
| 74x1G07
| 1个 [[buffer gate]]
| schmitt trigger
| open-drain
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G07.pdf LVC]
|-
| 74x1G08
| 1个 2输入 [[AND gate]]
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G08.pdf LVC]
|-
| 74x1G09
| 1个 2输入 AND与门
|
| open-drain
| 5
| [https://assets.nexperia.com/documents/data-sheet/74AUP1G09.pdf AUP]
|-
| 74x1G10
| 1个 3输入 NAND与非门
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G10.pdf LVC]
|-
| 74x1G11
| 1个 3输入 AND与门
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G11.pdf LVC]
|-
| 74x1G14
| 1个 非门
| schmitt trigger
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G14.pdf LVC]
|-
| 74x1G17
| 1个 buffer gate
| schmitt trigger
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G17.pdf LVC]
|-
| 74x1G18
| 1个 1-of-2 non-inverting [[multiplexer]], deselected output is 3-state
|
| [[三态逻辑|三态逻辑]]
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G18.pdf LVC]
|-
| 74x1G19
| 1个 1-to-2 [[line decoder]], active low outputs
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G19.pdf LVC]
|-
| 74x1G27
| 1个 3输入 NOR 或非门
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G27.pdf LVC]
|-
| 74x1G29
| 1个 2-to-3 line decoder, active low outputs
|
|
| 8
| [http://www.ti.com/lit/gpn/sn74lvc1g29 LVC]
|-
| 74x1G32
| 1个 2输入 [[OR gate]]
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G32.pdf LVC]
|-
| 74x1G34
| 1个 buffer gate
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G34.pdf LVC]
|-
| 74x1G38
| 1个 2输入 NAND与非门
|
| open-drain
| 5
| [https://assets.nexperia.com/documents/data-sheet/74AUP1G38.pdf LVC]
|-
| 74x1G57
| 1个 configurable 7-function gate
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G57.pdf LVC]
|-
| 74x1G58
| 1个 configurable 7-function gate
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G58.pdf LVC]
|-
| 74x1G66
| 1个 SPST analog switch
| analog
| analog
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G66.pdf LVC]
|-
| 74x1G74
| 1个 D-type [[Flip-flop (electronics)|flip-flop]], positive-edge trigger, Q & {{overline|Q}} outputs, asynchronous preset and clear
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G74.pdf LVC]
|-
| 74x1G79
| 1个 D-type flip-flop, positive-edge trigger, Q output
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G79.pdf LVC]
|-
| 74x1G80
| 1个 D-type flip-flop, positive-edge trigger, {{overline|Q}} output
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G80.pdf LVC]
|-
| 74x1G86
| 1个 2输入 [[XOR gate]] ([[also known as|a.k.a.]] 2-bit even-[[Parity (mathematics)|parity generator]])
|
|
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G86.pdf LVC]
|-
| 74x1G97
| 1个 configurable 7-function gate
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G97.pdf LVC]
|-
| 74x1G98
| 1个 configurable 7-function gate
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G98.pdf LVC]
|-
| 74x1G99
| 1个 configurable 15-function gate, active-low enable
| schmitt trigger
| 三态逻辑
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G99.pdf LVC]
|-
| 74x1G123
| 1个 retriggerable [[monostable]] multivibrator, active-low clear
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G123.pdf LVC]
|-
| 74x1G125
| 1个 buffer gate, active-low enable
|
| 三态逻辑
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G125.pdf LVC]
|-
| 74x1G126
| 1个 buffer gate, active-high enable
|
| 三态逻辑
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G126.pdf LVC]
|-
| 74x1G132
| 1个 2输入 NAND与非门
| schmitt trigger
|
| 5
| [http://www.ti.com/lit/gpn/sn74lvc1g132 LVC]
|-
| 74x1G139
| 1个 2-to-4 line decoder, active low outputs
|
|
| 8
| [http://www.ti.com/lit/gpn/sn74lvc1g139 LVC]
|-
| 74x1G157
| 1个 2输入 multiplexer
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G157.pdf LVC]
|-
| 74x1G158
| 1个 2输入 multiplexer, inverted output
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74AUP1G158.pdf AUP]
|-
| 74x1G175
| 1个 D-type flip-flop, positive-edge trigger, Q output, asynchronous clear
|
|
| 6
| [http://www.ti.com/lit/ds/symlink/sn74lvc1g175.pdf LVC]
|-
| 74x1G240
| 1个 非门, active-low enable
|
| 三态逻辑
| 5
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G240.pdf LVC]
|-
| 74x1G332
| 1个 3输入  OR或门
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G332.pdf LVC]
|-
| 74x1G373
| 1个 D-type transparent latch, negative-edge latching, Q output, active-low enable
|
| 三态逻辑
| 6
| [http://www.ti.com/lit/gpn/sn74lvc1g373 LVC]
|-
| 74x1G374
| 1个 D-type flip-flop, positive-edge trigger, Q output, active-low enable
|
| 三态逻辑
| 6
| [http://www.ti.com/lit/gpn/sn74lvc1g374 LVC]
|-
| 74x1G386
| 1个 3输入 XOR异或门 (a.k.a. 3-bit even-parity generator)
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC1G386.pdf LVC]
|-
| 74x1G0832
| 1个 3输入 AND-OR combo gate (2输入 AND into 2输入 OR)
| schmitt trigger
|
| 6
| [http://www.ti.com/lit/gpn/sn74lvc1g0832, LVC]
|-
| 74x1G3157
| 1个 SPDT analog switch
| analog
| analog
| 6
| [http://www.ti.com/lit/gpn/sn74lvc1g3157 LVC]
|-
| 74x1G3208
| 1个 3输入 OR-AND combo gate (2输入 OR into 2输入 AND)
| schmitt trigger
|
| 6
| [http://www.ti.com/lit/gpn/sn74lvc1g3208 LVC]
|}
 
===Two-gate chips===
All chips in this section have two gates, noted by the "2G" in the part numbers.
 
{|class="wikitable sortable"
! 芯片型号 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x2G00
| 2个 2输入 NAND与非门
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G00.pdf LVC]
|-
| 74x2G02
| 2个 2输入 NOR 或非门
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G02.pdf LVC]
|-
| 74x2G04
| 2个 非门
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G04.pdf LVC]
|-
| 74x2G06
| 2个 非门
| [[schmitt trigger]]
| [[Open drain|open-drain]]
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G06.pdf LVC]
|-
| 74x2G07
| 2个 buffer gate
| schmitt trigger
| open-drain
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G07.pdf LVC]
|-
| 74x2G08
| 2个 2输入 AND与门
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G08.pdf LVC]
|-
| 74x2G14
| 2个 非门
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G14.pdf LVC]
|-
| 74x2G17
| 2个 buffer gate
| schmitt trigger
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G17.pdf LVC]
|-
| 74x2G32
| 2个 2输入  OR或门
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G32.pdf LVC]
|-
| 74x2G34
| 2个 buffer gate
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G34.pdf LVC]
|-
| 74x2G38
| 2个 2输入 NAND与非门
|
| open-drain
| 8
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G38.pdf LVC]
|-
| 74x2G57
| 2个 configurable 7-function gate
| schmitt trigger
|
| 10
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G57.pdf AUP]
|-
| 74x2G58
| 2个 configurable 7-function gate
| schmitt trigger
|
| 10
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G58.pdf AUP]
|-
| 74x2G66
| 2个 SPST analog switch
| analog
| analog
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G66.pdf LVC]
|-
| 74x2G79
| 2个 D-type flip-flop, positive-edge trigger, Q output
|
|
| 8
| [http://www.ti.com/lit/gpn/sn74lvc2g79 LVC]
|-
| 74x2G80
| 2个 D-type flip-flop, positive-edge trigger, {{overline|Q}} output
|
|
| 8
| [http://www.ti.com/lit/gpn/sn74lvc2g80 LVC]
|-
| 74x2G86
| 2个 2输入 XOR异或门 (a.k.a. 2-bit even-parity generator)
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G86.pdf LVC]
|-
| 74x2G97
| 2个 configurable 7-function gate
| schmitt trigger
|
| 10
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G97.pdf AUP]
|-
| 74x2G98
| 2个 configurable 7-function gate
| schmitt trigger
|
| 10
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G98.pdf AUP]
|-
| 74x2G125
| 2个 buffer, active-low enable
|
| [[三态逻辑|三态逻辑]]
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G125.pdf LVC]
|-
| 74x2G126
| 2个 buffer, active-high enable
|
| 三态逻辑
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G126.pdf LVC]
|-
| 74x2G132
| 2个 2输入 NAND与非门
| schmitt trigger
|
| 8
| [http://www.ti.com/lit/gpn/sn74lvc2g132 LVC]
|-
| 74x2G240
| 2个 非门, active-low enable
|
| 三态逻辑
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G240.pdf LVC]
|-
| 74x2G241
| 2个 buffer, active-low and active-high enables
|
| 三态逻辑
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC2G241.pdf LVC]
|-
| 74x2G0604
| 2个 combo gates - one inverter, one inverter with O.D.
|
| open-drain
| 6
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G0604.pdf AUP]
|-
| 74x2G3404
| 2个 combo gates - one buffer, one inverter
|
|
| 6
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G3404.pdf AUP]
|-
| 74x2G3407
| 2个 combo gates - one buffer, one buffer with O.D.
|
| open-drain
| 6
| [https://assets.nexperia.com/documents/data-sheet/74AUP2G3407.pdf AUP]
|}
 
===Three-gate chips===
All chips in this section have three gates, noted by the "3G" in the part numbers.
 
{|class="wikitable sortable"
! 芯片型号 !! 描述 !! 输入 !! 输出 !! Pin数目 !! 数据手册
|-
| 74x3G04
| 3个 非门
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC3G04.pdf LVC]
|-
| 74x3G06
| 3个 非门
| [[schmitt trigger]]
| [[Open drain|open-drain]]
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC3G06.pdf LVC]
|-
| 74x3G07
| 3个 buffer gate
| schmitt trigger
| open-drain
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC3G07.pdf LVC]
|-
| 74x3G14
| 3个 非门
| schmitt trigger
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC3G14.pdf LVC]
|-
| 74x3G16
| 3个 buffer gate
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC3G16.pdf LVC]
|-
| 74x3G17
| 3个 buffer gate
| schmitt trigger
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC3G17.pdf LVC]
|-
| 74x3G34
| 3个 buffer gate
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74LVC3G34.pdf LVC]
|-
| 74x3G0434
| 3个 combo gates - two inverter, one buffer
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74AUP3G0434.pdf AUP]
|-
| 74x3G3404
| 3个 combo gates - two buffer, one inverter
|
|
| 8
| [https://assets.nexperia.com/documents/data-sheet/74AUP3G3404.pdf AUP]
|}
 
===Voltage translation===
All chips in this section have '''two''' power-supply pins to translate unidirectional logic signals between two different logic voltages. The logic families that support 2个-supply voltage translation are AVC, AVCH, AXC, AXCH, AXP, LVC, where the "H" in AVCH and AXCH means "bus hold" feature.
 
{|class="wikitable sortable"
! 芯片型号 !! 描述 !! Pin数量 !! AXC !! AXP !! LVC
|-
| 74x1T45
| 1 buffer
| 6
| [https://www.ti.com/lit/gpn/SN74AXC1T45 AXC]
| [https://www.nexperia.com/products/analog-logic-ics/asynchronous-interface-logic/voltage-translators-level-shifters/series/74AXP1T45.html AXP]
| [https://www.ti.com/lit/gpn/SN74LVC1T45 LVC]
|-
| 74x2T45
| 2 buffers
| 8
| [https://www.ti.com/lit/gpn/SN74AXC2T45 AXC]
| [https://www.nexperia.com/products/analog-logic-ics/asynchronous-interface-logic/voltage-translators-level-shifters/series/74AXP2T45.html AXP]
| [https://www.ti.com/lit/gpn/SN74LVC2T45 LVC]
|-
| 74x4T245
| 4 buffers
| 16
| [https://www.ti.com/lit/gpn/SN74AXC4T245 AXC]
| [https://www.nexperia.com/products/analog-logic-ics/asynchronous-interface-logic/voltage-translators-level-shifters/series/74AXP4T245.html AXP]
| style="background: grey; text-align: center;" | n/a
|-
| 74x8T245
| 8 buffers
| 24
| [https://www.ti.com/lit/gpn/SN74AXC8T245 AXC]
| [https://www.nexperia.com/products/analog-logic-ics/asynchronous-interface-logic/voltage-translators-level-shifters/series/74AXP8T245.html AXP]
| [https://www.ti.com/lit/gpn/SN74LVC8T245 LVC]
|-
| 74x16T245
| 16 buffers
| 48
| style="background: grey; text-align: center;" | n/a
| style="background: grey; text-align: center;" | n/a
| [https://www.ti.com/lit/gpn/SN74LVC16T245 LVC]
|}
 
Chips in the above table support the following voltage ranges on either power supply pin:
* AXC = 0.65 to 3.6&nbsp;V. Only available from Texas Instruments.
* AXP = 0.9 to 5.5&nbsp;V. Only available from Nexperia.
* LVC = 1.65 to 5.5&nbsp;V. Available from Diodes Inc, Nexperia, Texas Instruments.
 
==See also==
* [[4000-series integrated circuits]]
* [[List of 4000-series integrated circuits]]
* [[Push–pull output]], [[Open collector|Open-collector output]], [[Three-state logic|Three-state output]]
* [[Schmitt trigger|Schmitt trigger input]]
* [[Logic gate]], [[Logic family]]
* [[Programmable logic device]]
* [[Pin compatibility]]
 
==References==
{{Reflist}}
 
==Further reading==
{{See also|7400-series integrated circuits#Further reading|l1=List of books about 7400-series integrated circuits}}
* Digital Integrated Circuits, [[National Semiconductor|National Semiconductor Corporation]], January 1974
* Logic/Memories/Interface/Analog/Microprocessor/Military Data Manual, [[Signetics|Signetics Corporation]], 1976
* The Bipolar Microcomputer Components Data Book for Design Engineers, Second Edition, [[Texas Instruments]], 1979
* The TTL Data Book for Design Engineers, Second Edition, [[Texas Instruments]], 1976
* Bipolar LSI 1982 Databook, [[Monolithic Memories|Monolithic Memories Incorporated]], September 1981
* Schottky TTL Data, DL121R1 Series D Third Printing, [[Motorola]], 1983
* High-Speed CMOS Logic Data Book, [[Texas Instruments]], 1984
* [http://www.ti.com/lsds/ti/logic/home_overview.page Logic: Overview], [[Texas Instruments]] Incorporated
* [http://focus.ti.com/lit/ug/sced006b/sced006b.pdf ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)], [[Texas Instruments]], 2002
* IC Master, 1976
* Schottky and Low-Power Schottky Data Book, [[Advanced Micro Devices]], July 1978
 
{{DEFAULTSORT:7400 TTL}}
[[Category:Digital electronics|7400]]
[[Category:Electronic design]]
[[Category:Electronics lists]]
[[Category:Integrated circuits|7400]]

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